當半導體的製程進入奈米的等級後，製程變異的影響 (process variation) 讓晶片在量產時，晶片的良率持續地惡化。在這篇論文中，我們提出一個以列電壓調控為基礎的可調式電路設計機制 (row-based tunable design)。利用此機制，使用者可以逐列地調整工作電壓 (supply voltage) 與基底電壓 (body bias)。這篇論文所使用的方法，是利用微調工作電壓，來修正下線後不符合規格的晶片，以減輕製程變異的影響。在我們的方法中，由於不同電壓的差距夠小，因此在高工作電壓與低工作電壓區域之間，不需要使用階層轉換器電路 (level conversion)。為了簡化設計的流程並減輕電路設計者的負擔，我們在自動繞線佈局 (auto-placement-and-route, APR) 的流程中，將變更電路設計的步驟自動化，並且讓這個變更電路的流程完全相容於現有的 cell-based 電路設計流程。

在實驗中，我們將可調式電路實作在180奈米製程上，並建立原型電路以提供模擬。在s9234可調式原型電路中，我們模擬所有可用的工作電壓與基底電壓的組合。發現以節省功率為目標的最佳電壓組合，可以節省漏電流功率達98%，且可節省的最佳動態功率可以達22%。而以電路延遲為目標的最佳電壓配置中，電路的路徑延遲平均可以減少19%，而且也可以將路徑延遲的分布集中20%。在電路面積使用方面，可調式元件所占面積小於整體電路面積5%，如果將電源閘控電路包含在內，在大型電路中所使用的面積比例約為整體電路的10%。

As the CMOS technology coming to nanometer scale, process variation increasingly deteriorates the yield of mass production. Here we propose to employ a row-based tunable design methodology which allows users to adjust the supply voltage, as well as the body bias. The method presented in this thesis is able to mitigate the effect of process variation by fine-tuning the supply voltages for fabricated chips that fail the expected specification. In our method, the voltage difference between rows is small enough so that the level conversion is not required between lower supply voltage cells and higher ones. In order to facilitate design process and reduce designers' efforts, we automate the process of modifying designs at the auto-placement-and-route (APR) stage. The modified flow is completely compatible to the currently adopted cell-based design flow.

In the experiments, we have applied our method on 180nm process node, and constructed a prototype of the tunable circuit. Then, the area estimation shows that the area overhead of the tunable components is less than 5%. Even including the power gating circuits, the total area overhead is just about 10% in large benchmarks. In all configurations of supply voltages and body biases, the best leakage and dynamic power savings of the tunable s9234 benchmark are 98% and 22%, respectively. Moreover, the path delays is reduced by 19% on average, and the deviation of path delay distribution tightened 20% for the best case.

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