應用於高速序列傳輸系統之操作在20-GHz的高解析度數位式鎖相迴路

簡易檢索 / 詳目顯示

回結果列表

研究生：	郭雅瑄 Kuo, Ya-Hsuan
論文名稱：	應用於高速序列傳輸系統之操作在20-GHz的高解析度數位式鎖相迴路 A 20-GHz Digital Phase-Locked Loop with High-Resolution for High-Speed Serial Links
指導教授：	朱大舜 Chu, Ta-Shun 彭朋瑞 Peng, Pen-Jui
口試委員:	王毓駒 Wang, Yu-Jiu 吳仁銘 Wu, Jen-Ming
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2023
畢業學年度：	111
語文別：	英文
論文頁數：	95
中文關鍵詞：	數位式鎖相迴路、數位式三角積分調變器、二階雜訊移頻
外文關鍵詞：	Digital Phase-Locked Loop, Digital Delta-Sigma Modulator, MASH 1-1
相關次數：	點閱：43 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

　　本研究以TSMC 65nm CMOS製程設計一個操作在20GHz頻率下的數位控制鎖相迴路，透過數位邏輯的優化來達到更快速、高精細度以及低耗能的需求，該電路主要由非線性一位元式相位偵測器(BBPD)、數位濾波器(DLF)、二階數位三角積分調變器(MASH1-1 DDSM)與解碼器(B-to-T Decoder)、使用嵌入式數位類比轉換器架構的壓控振盪器和串接除頻器組成。

　　一位元式相位偵測器可以達到低功耗和佈局面積較小的需求。而在數位濾波器上使用了改良架構以有效降低計算的延遲時間。但在嵌入式數位類比轉換器架構上使用的電路為多位元的切換電容陣列，因此數位控制振盪的調頻的最小變異量會受到製程的限制，為了克服此問題，採用二階數位三角積分調變器用來輸出平均等效為小數型的數位控制碼，來得到更精細的數位控制震盪調頻解析度。

　　本研究實現的數位控制振盪器的相位雜訊為-120dBc/Hz，而整體鎖相迴路系統的可調變頻率在19.46-GHz至20.49GHz之間，頻率調諧比例(FTR)約為5.16%，而峰對峰值抖動約為1.4ps，整體的功率消耗為19.2mW，核心電路佈局面積為0.08mm2。

　In this research, a digital phase-locked loop (DPLL) operating at 20 GHz is implemented using a 65 nm CMOS process. Through optimization of digital logic, higher speed, precision, and lower power consumption is achieved. The circuit includes a nonlinear phase detector (BBPD), digital loop filter (DLF), digital ΔΣ Modulator (MASH1-1 DDSM), decoder (B-to-T Decoder), and a digitally controlled oscillator (DCO) and frequency dividers (DIV).

　The BBPD design meets requirements for low power consumption and a smaller layout area. Additionally, an improved structure is used for the DLF to effectively reduce computation delay. However, the switching capacitor array limits the frequency resolution of the DCO. Therefore, a MASH1-1 DDSM is employed to output an equivalent fraction-type digital control code.

　The implemented DCO exhibits a phase noise of -120 dBc/Hz. The overall system allowed adjustable frequency within the range of 19.46 GHz to 20.49 GHz, with a frequency tuning ratio (FTR) of approximately 5.16%. The peak-to-peak jitter is measured to be around 1.4 ps, and the overall power consumption is 19.2 mW. The core circuit layout occupies an area of 0.08 mm2.

摘要 i
Abstract ii
誌謝 iii
Contents iv
List of Figures vi
List of Tables ix

Chapter1 Introduction 1
1 Introduction to chapters 1
2 Background 1
3 PLL in communication system 3
4 Analysis of PLL system 4
4.1 Type-I PLL 7
4.2 Charge pump PLL 9
4.3 Digital PLL 11
5 Time-domain analysis 15
6 Noise in DPLL 19
6.1 Flicker noise and white Noise 19
6.2 Phase noise in PLLs 20

Chapter2 Digital-PLL Building Block 25
1 Oscillator 25
1.1 Ring Oscillator 26
1.2 LC Oscillator 28
1.3 Frequency tuning 32
1.4 DCO implementations 34
1.5 Phase noise and Jitter 37
2 Phase Detector 39
2.1 Time-to-Digital Converter 39
2.2 Nonlinear Phase Detector 41
3 Frequency Divider 43
3.1 Multi-Modulus Divider 43
3.2 Divider Cell 44
4 Digital Loop Filter 46
4.1 IIR filters 47
4.2 Digital Accumulator 49

Chapter3 Circuit Implementation of a 20GHz Digital-PLL with High Resolution 50
1 Design of the system parameter 53
2 Nonlinear Phase Detector 55
3 11bits Digital Loop Filter 56
3.1 Two path implementations 56
3.2 An efficient increment/decrement circuit 57
3.3 Mux 60
4 Binary-to-Thermometer Decoder 62
5 Multi-Stage Noise-Shaping Delta-Sigma Modulator 64
6 LC Oscillator with Embedded-DAC 71
7 Cascaded Frequency Divider 74
7.1 Current-Mode Logic 75
7.2 True Single-Phase Clock 77
7.3 Static CMOS Logic 78

Chapter4 Experimental Results of the 20GHz DPLL 80
1 20GHz Digital-Controlled LC-Oscillator 80
2 Digital control code 83
3 System Simulation 87
4 Circuit Layout of the DPLL 87
5 Performance Table 92

Chapter5 Conclusion and Improvement 93

Reference 94


                                

[1] D. Pfaff, R. Abbott, X.-J. Wang, S. Moazzeni, R. Mason and R.R. Smith, "A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS," in IEEE Journal of Solid-State Circuits, March 2020.

[2] S.-Y. Yang, W.-Z. Chen and T.-Y. Lu, "A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology," in IEEE Journal of Solid-State Circuits, March 2010.

[3] J. Kim et al., "16.2 A 76fsrms Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization," 2019 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, 2019.

[4] M. Mercandelli et al., "17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter," 2020 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2020.

[5] S. Kalia et al., "A Sub-100 Fs RMSjitter 20 GHz Fractional-N Analog PLL With a BAW Resonator Based On-Chip 2.5 GHz Reference," in IEEE Journal of Solid-State Circuits, May 2022.

[6] Razavi, Behzad. Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level. 1st ed., 2020.

[7] Razavi, Behzad. RF MICROELECTRONICS. Second Edition, 2011.

[8] Deog-Kyoon Jeong. “Introduction to All-Digital PLL.” Integrated Systems Design Laboratory Seoul National University.

[9] T.-K. Kuan and S.-I. Liu, "A Bang Bang Phase-Locked Loop Using Automatic Loop Gain Control and Loop Latency Reduction Techniques," in IEEE Journal of Solid-State Circuits, April 2016.

[10] G.-M. Luo and C.-Y. Yang, "A 10-GHz Fast-Locked All-Digital Frequency Synthesizer with Frequency-Error Detection," 2019 32nd IEEE International System-on-Chip Conference (SOCC), Singapore, 2019.

[11] A. Rylyakov et al., "Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications," 2009 IEEE International Solid-State Circuits Conference, 2009.

[12] V. Kratyuk, P. K. Hanumolu, U.-K. Moon and K. Mayaram, "A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy," in IEEE Transactions on Circuits and Systems II, March 2007.

[13] D.-W. Jee, Y.-H. Seo, H.-J. Park and J.-Y. Sim, "A 2 GHz Fractional-N Digital PLL with 1b Noise Shaping ΔΣ TDC," in IEEE Journal of Solid-State Circuits, April 2012.

[14] C.-C. Hung and S.-I. Liu, "A 40-GHz Fast-Locked All-Digital Phase-Locked Loop Using a Modified Bang-Bang Algorithm," in IEEE Transactions on Circuits and Systems II: Express Briefs, June 2011.

[15] J.-M. Lin and C.-Y. Yang, "A Fast-Locking All-Digital Phase-Locked Loop with Dynamic Loop Bandwidth Adjustment," in IEEE Transactions on Circuits and Systems I: Regular Papers, 2015.

[16] T. Lee, Y.-H. Kim, J. Sim, J.-S. Park and L.-S. Kim, "A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery with Hybrid Dithering Using a Time-Dithered Delta–Sigma Modulator," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, April 2016.

[17] L. Bertulessi, D. Cherniak, M. Mercandelli, C. Samori, A.L. Lacaita and S. Levantino, "Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise," in IEEE Transactions on Circuits and Systems I: Regular Papers, May 2022.

[18] G.-M. Luo and C.-Y. Yang, "A 10-GHz Fast-Locked All-Digital Frequency Synthesizer with Frequency-Error Detection," 2019 32nd IEEE International System-on-Chip Conference (SOCC), Singapore, 2019.

[19] E. Thaller et al., "32.6 A K-Band 12.1-to-16.6GHz Subsampling ADPLL with 47.3fsrms Jitter Based on a Stochastic Flash TDC and Coupled Dual-Core DCO in 16nm FinFET CMOS," 2021 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2021.

[20] G.-Y. Su, Z.-H. Kang and S.-I. Liu, "An Adaptive Loop Gain Tracking Digital PLL Using Spectrum-Balancing Technique," 2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan, 2021.

[21] L. Xian, L. Wenyuan and W. Zhigong, "A wide tuning range LC-VCO using switched capacitor array technique," 2010 International Symposium on Signals, Systems and Electronics, Nanjing, China, 2010.

[22] Yilong Liao, Xiangning Fan, “Spur-free MASH DDSM with Eliminable Dither “Institute of RF&OE-ICs, School of Information Science and Engineering, Southeast University, Nanjing, China, 2017.

[23] S. Tertinek, J.P. Gleeson and O. Feely, "Binary Phase Detector Gain in Bang-Bang Phase-Locked Loops With DCO Jitter," in IEEE Transactions on Circuits and Systems II, 2010.

簡易檢索 / 詳目顯示

相關論文