在現今高效能導向的電腦架構下，部記憶體扮演越來越重要的角色,甚至會
影響到整體的運算速度，在目前的系統單晶片(SoC)架構設計時 常會配合使用電
子系統層級(ESL)層級來營造軟硬體共同設計的環境，因此一個準確並且快速的
外部記憶體系統模型成為架構設計者不可或缺的角色。我們利用電子系統層級做
為模型設計，並且利用一個外部記憶體模擬器(DRAMSim2)為基礎，建立出一個
SystemC/OCP 環境的模型。由於 DRAMSim2 提供複雜的記憶體控制器(Memory Controller)機制，再加上DRAMSim2 對於模擬的時間精細度到達時脈精準(Cycle-Accurate)，過多不影響模擬結果的時脈以及機制被模擬出來，因此整體的模擬速度會偏慢。本篇論文中，我們提出一個基於 DRAMSim2 的外部記憶模型，利用 SystemC所提供的程序(Process)以及事件(Event)建立出一個事件驅動的模型，程序彼此間利用事件做為溝通，如此時間精細度不是時脈精準，但是由於只模擬有意義的時間點，因此對於模擬正確性而言不會受到影響，但可進而加快模擬速度。對於驗證方面，記錄下每一個外部記憶體活動的時間點與動作，必較DRAMSim2 所建立的 SystemC 模型與我們所提出基於事件模型，我們利用 Spec CPU 2006 為我們的驗證追蹤檔案(Trace File)，在所有的 Trace File 中驗證過我們所提出的事件驅動模型是正確的。實驗結果顯示，本論文所提出的方法可以增快模擬速度從 1.8 倍到 14 倍，增快的速度取決於 Trace File 中記憶體指令的密度。

For computer system design, accurate modeling and fast simulation of external memories (DRAMs) are key to achieve high performance and efficiency. To adapt the simulation of DRAMs in Electronic System Level design, we study and wrap an existing simulator (DRAMSim2) in the SystemC/OCP environments. Though DRAMSim2 support sophisticated mechanism of DRAM controllers, the simulation works to handle all activities in a cycle-based behavior. Therefore, the idle cycles and activities with long cycles may not be handled efficiently. In this thesis, we proposed an event-based DRAM simulation scheme to address this issue (or more precisely based on SystemC process and events). To verify the proposed ESL model, we constructed test benches based on memory traces (extracted from SPEC CPU2006). For all test benches, the simulated cycles are identical for both simulators and the event-based model is about 1.8x to 14x faster than DRAMSim2-based model.

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