應用於90nm CMOS 製程之V頻帶Doherty功率放大器—分析與實務製作

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研究生：	朱緯東 Chu, Wei-Tung
論文名稱：	應用於90nm CMOS 製程之V頻帶Doherty功率放大器—分析與實務製作 V-band Doherty Power Amplifier in 90nm CMOS Technology—Analysis and Implementation
指導教授：	劉怡君 Liu, Yi-Chun
口試委員:	徐碩鴻 Hsu, Shuo-Hung 李俊興 Li, Chun-Hsing
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2018
畢業學年度：	106
語文別：	英文
論文頁數：	186
中文關鍵詞：	毫米波、功率放大器、峰均功率比、阻抗調變、功率附加效率、功率倒退
外文關鍵詞：	load modulation, power-added efficiency, Back-off
相關次數：	點閱：4 下載：0
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近年來，高傳輸速率的系統日益趨增，毫米波頻段也因為非常寬頻的原因而被發展起來，也越來越多的無線通訊應用在這具有發展淺力的頻段日益茁壯。
在通訊系統方面，會用調變技術(Modulation Technique)對傳遞訊號做適當的調整，使其整體通訊方面更加優化。然而，調變技術會使訊號有很高的峰對均功率比值(Peak-to-Average Power Ratio, PAPR)，故需要以倒退功率(Output Power Back-Off, OBO)的方式來補償線性度，此時的PAE會低落許多，將導致供應功率放大器的電池使用壽命減少許多，為了能最有效的使用功率放大器，Back-Off PAE是必須考慮的一項指標。於是Doherty功率放大器為了這個目的而被發展。
此 60 GHz Doherty功率放大器電路由class AB 功率放大器與class C功率放大器所組成，並且以經替換架構後的等效λ/4傳輸線來實現class AB 功率放大器阻抗調變(Load Modulation)與功率結合的角色，同時為了達成兩路輸出功率為同相位輸出(In-Phase)，相位補償也有考慮的必要性，最後在輸入的部分以直接功率分工器(Direct Power Divider) 做等功率分路。
本電路模擬在輸出功率為8.674 dBm 時，具有最高PAE為7.988 %，DC功率為25.63 mW，並於4.988 dB Back-off處具有次峰PAE值為6.517 %，DC功率為13.79 mW。
量測結果尚有2.5 dB的功率倒退空間，功率倒退及峰值PAE分別為7.288 % 和7.89 %，6 B功率倒退處為3.64 %，在峰值PAE處輸出功率為6.84 dBm。

With the demands for high-speed data transmission, the millimeter-wave frequency band is developed because of its wider bandwidth. More and more applications are focused on this potential frequency band.
In communication systems, modulation schemes are widely used for better data rates or other better performance. However, there is high peak-to-average ratio (PAPR) for modulated signal. So the output power back-off (OBO) is used to compensate linearity. In this operation mode, power-added-efficiency (PAE) is much more worse than before. It may shorten the lifetime of power amplifiers (PAs). In order to use PA more effectively, back-off PAE is the specification to be notify. Hence, Doherty PA has been developed till now.
A 60 GHz Doherty PA with the combination of class AB PA and class C PA is purposed. The alternated structure of λ/4 transmission line is used to deal with load modulation for class AB PA and power combination for both PA. In order to achieve in-phase for combining path, phase compensation is also needed after the load modulation network and power combiner. Direct power divider is inserted for the input terminals of both PAs for equal power-division.
The simulated 60 GHz Doherty PA achieves maximum PAE as 7.988 % at 8.674 dBm output power. 25.63 mW with DC consumption is needed to operate at this power level. At 4.988 dB back-off point, back-off PAE is 6.517 % with 13.79 mW DC consumption.
From the measurement, the proposed 60 GHz Doherty PA shows an output back-off range of 2.5 dB. Back-off and peak PAE are 7.288 % and 7.89 %, respectively. PAE at 6 dB back-off is 3.64 %. P_L at peak PAE is 6.84 dBm.

Acknowledgement    I
中文摘要    III
ABSTRACT    IV
Contents    V
List of Figures    VIII
List of Tables    XIX
Chapter I Introduction    1
1 Motivation    1
2 V-band Standards and Applications    2
3 Thesis Organization    4
Chapter II Overview of Power Amplifiers    5
1 Introduction    5
2 Power Amplifier Specifications    5
2.1 Output Power    5
2.2 Linearity    6
2.3 Efficiency    8
3 Single-Stage Power Amplifiers    10
3.1 Classifications of Power Amplifiers and Knee Voltage Effect    10
3.2 ft and fmax    16
3.3 Stability    18
4 Passive Devices    21
4.1 Inductors    21
4.2 Transmission Lines    24
4.3 Matching Network    30
Chapter III Doherty Power Amplifier Theory and Analysis    36
1 Background    36
2 Basic Operating Principle    38
2.1 Impedance Variation for Individual Power Amplifier    38
2.2 Clarification for Load Modulation    42
2.3 Conventional Load-Modulated Solution and Performance of Doherty Power Amplifier    47
3 Qusai-Load Line and Selection of MOS device    57
3.1 Quasi-Load Line Extraction    57
3.2 Comparison of Sizes of MOSFET and Bias Conditions    60
3.3 Qusai-Load Line of Doherty PA    70
4 Doherty Power Amplifier Optimum Point Selection    78
4.1 Low-Power Mode and High-Power Mode Optimum Point Selection    78
4.2 Peaking Power Amplifier OFF-State Condition    82
5 Load Modulation Realization    86
5.1 Conventional Method    86
5.2 Offset Line Method    90
5.3 Transformer Less Load Modulation Method (TLLM)    108
5.4 Modified Network    113
6 Power Dividers    143
6.1 Wilkinson Power Dividers    143
6.2 Direct Power Dividers    148
Chapter IV Doherty Power Amplifier Implementation    150
1 Carrier Power Amplifier with Output Terminal    150
2 Peaking Power Amplifier with Two-Sided Network    155
3 Phase Compensation by Input Matching    158
4 Wilkinson Power Divider and Direct Power Divider    163
5 Simulation and Measurement Results    170
Chapter V Conclusion and Future Works    182
References    183

                                

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