一般快閃式記憶體的操作都是應用通道熱載子注入或福樂-諾漢穿隧效應導致電子注入的方式，然而這些操作都是需要高電壓，因此快閃式記憶體的升壓電路為週邊電路中極為重要的一環。此外，近年來攜帶型個人電子產品盛行，使得嵌入式的快閃記憶體成了近年來研究的重點。由於舊型的金氧半導體元件或二極體升壓電路大都是運用三井的製程以及較厚的氧化層來隔絕升壓電路所產生的高電壓，使得接面崩潰電壓以及閘極到通道崩潰電壓都比一般在邏輯製程單井下的互補式金氧半導體來的大的多，所以崩潰的情形不會發生在升壓電路操作時。因此嵌入式快閃記憶體的升壓電路為了與周邊的電晶體的製程相容，將無法使用抗高壓的電路元件，因此傳統的升壓電路將無法在高壓操作，將面臨電路元件崩潰的情形。
本篇論文將提出一種新型的升壓電路，利用電容串接的方式將每個節點的電壓差控制在兩倍輸入電壓內，如此一來，此種升壓電路可以應用在單井的製程之下不會有接面崩潰或氧化層崩潰的情形產生。

此升壓電路也將利用P型金氧半導體來操作，經由基極與汲極的連接來克服傳統電路的基極效應，提供更高的輸出電壓與較佳的效率。並將電路的層級、輸出電壓與電晶體寬度做最佳化。並提出不同的架構用以提高輸出電流，以及提昇充電的時間，用以應用在不同的記憶體單元的操作機制上。

Flash memory cells require high voltage for program and erase operations. These high voltages are generated by charge pump circuits with low supply voltage. Therefore charge pumping circuit is one of the most important peripheral elements in flash memory. In recent years, portable electronic products to meet the popular demand of embedded flash become the key interest of researches and memory design house. Using standard low-voltage logic IC process, no high voltage devices are available. This creates a problem for the conventional charge pumping circuit, which allows high voltage across transistor terminals.
This thesis provides one new charge pump circuit to solve this issue. It uses serial connected capacitors to control voltage difference between device terminals to less than 2Vdd. The new circuit fabricated in single well process can provide the high voltage for Flash memory operation and does not suffer from junction or gate oxide breakdowns. In order to avoid body effect, PMOS devices are adapted, which allows body, drain and gate to be tired together to overcome body effect. Higher output voltage and higher efficiency of the new circuit configuration are demonstrated. Optimization of the channel width, stage and output voltage for various Flash cell operation are presented.

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[2] T. Tanzawa and S. Atsumi, “Optimization of Word-Line Booster Circuits for Low-Voltage Flash Memories,” IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 8, pp.1091-1098, AUGUST 1999.
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