H.264/AVC 是目前最新的壓縮標準，相較於現今的壓縮標準，H.264在傳輸量的節省與編碼失真的控制上都有顯著的改善，特別是在影像的壓縮和完全支援強健的傳輸在網路上。同時，在同樣的影像品質之下，它的比特率(bit-rate)比MPEG-2和MPEG-4分別少60%和40%。我們知道H.264擁有很高的影像壓縮效率，所以它可以應用在許多的方向。例如:高畫質的DVD、數位電視、數位攝影機、影像電話、網路的影像傳輸等等…。但是它的複雜編碼處理使得即時編碼應用的可行性不受到保證，以及龐大的運算量會造成嚴重的功率消耗，因此H.264 將面臨極大的挑戰，縱使擁有優秀的效能，但在謹慎的觀點下會使它無法普遍應用。
本報告首要目標是最佳化H.264/AVC CAVLC編碼端與解碼架構，利用改變Look Up table 的結構進而達到降低硬體的面積及加速編碼與解碼的速度，設計彈性化的架構以利輕易的重組來符合各種應用的需求，且同時擁有即時編碼能力。在本篇論文的結論中可得到兩個結果:在編碼端每一個四乘四的餘數方塊可以節省2~27的時間週期。第一：是我們使用16個比較器來找出第一個不為零的係數位置，在這可以節省0~15的時間週期。第二:是我們利用Zero-tree來對編碼表(coeff_token table)做適當的編排，是利用機率來做編排將機率最高的放在第一個表和次高的第二個表以此類推共四個表，在這可以節省2~12的時間週期。第三:是我們改變了可變長度編碼表(VLC table)的結構進而達到節省硬體的面積和利用重新編排編碼表(coeff_token table)來達到加速的目的。而在解碼端每一個四乘四的餘數方塊可以節省2~12的時間週期。最主要的是我們利用Zero-tree來對編碼表做適當的編排是與編碼端相同的原理，在這可以節省2~12的時間週期。
我們利用Xilinx FPGA平台實驗驗證架構即時處理能力，根據架構模擬結果，可觀察到畫面經過編碼與解碼後基本上確保了能顯示穩定品質的畫面。

H.264/AVC is the latest video compression standard. It achieves a significant improvement in bit-rate saving and rate-distortion performance compared with all existing compression standards. It particularly concentrates on video compression and fully supports robust transmission over networks. At the same video quality, it could achieve about 60% bit-rate saving over MPEG-2, and about 40% bit-rate saving over MPEG-4. High compression efficiency of H.264 gradually attracts many industries to apply it for emerging applications such as High Definition DVD, Digital TV, Digital Camcorders, Camera Phone, Internet video streaming, and others. However, H.264’s complicated encoding process can not guarantee feasibility in real-time coding implementation; in addition, huge computation will cause huge power-consumption. Therefore, from a conservative view, it will face a big challenge for becoming unpopular even it has superior performance.
The objective of this thesis is to optimize the architectures of H.264AVC CAVLC.
We review Encoding/Decoding process and revise Look Up tables for saving memory and speeding up Encoding/Decoding process. Flexible architecture is designed such that the use of H.264 in different applications can be adjusted by easy-recombining, and it will also possess real-time coding capability. We can get a conclusion in our architecture design. In the Encoder, each 4x4 residual block can save 2~27 clk cycles. First, we use 16 comparators to find first nonzero coefficient that can save 0~15 clk cycles. Second, we used zero tree to separate the coefficient token table, which can save 2~12 clk cycles each 4x4 residual block. Third, we revise VLC tables for saving memory and intend to revise the Coeff_token table to speed up encoding process. We used zero tree to separate the table to let higher frequent codeword put in table1 and lower frequent codewords put in the other tables. The revised VLC tables and zero tree can be seen in Chapter 2. We need only store the min positive parts of the VLC tables and need only store VLC tables, instead of the original seven tables. In the Decoder, each 4x4 residual block can save 2~12 clk cycles. Because we used zero tree to separate the coefficient token table, which can save 2~12 clk cycles for each 4x4 residual block.
Xilinx FPGA platform simulation demonstrates the real-time capability of proposed H.264/AVC Encoding/Decoding architecture. From architecture simulation, we observe that videos pass through the CAVLC Encoding and Decoding in real time and ensure that displays stable decoded frames.

[1] ThomasWiegand, Gary J. Sullivan, Gisle Bjøntegaard, and Ajay Luthra, “Overview of the H.264/AVC Video Coding Standard”, IEEE Transactions on Circuits and Systems for Video Ttechnology, Vol. 13, No. 7, July 2003.
[2] Wiegand, T., Sullivan, G., Bjontegaard, G., and Luthra, A., “Overview of the H.264/AVC Video Coding Standard,” IEEE Transactions on Circuits and Systems For Video Technology, Vol. 13, No. 7, pp. 560-576, July 2003.
[3] Yong Ho Moon , Gyu Yeong Kim, and Jae Ho Kim “An efficient decoding of CAVLC in H.264/AVC video coding standard”, IEEE Transactions on Consumer Electronics, Volume .51, Issue 3, Aug 2005.
[4] Hsiu-Cheng, Chang, Chien-Chang Lin, and Jiun-In Guo “A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding”, IEEE International Symposium on Circuits and Systems, Vol. 6, No. 6, May 2005.
[5] Wu Di, Gao Wen, Hu Mingzeng, and Ji Zhenzhou “A VLSI architecture design of CAVLC decoder”, 5th International Conference on ASIC Proceedings. Volume 2, 21-24 Oct. 2003.
[6] Amer, I.; Badawy, W. and Jullien, G., “Towards MPEG-4 part 10 system on chip: a VLSI prototype for context-based adaptive variable length coding (CAVLC)”, IEEE Workshop on Signal Processing Systems, 2004. SIPS, 275-279, 2004
[7] Yeong-Kang Lai, Chih-Chung Chou, and Yu-Chieh Chung, “A simple and cost effective video encoder with memory-reducing CAVLC”, IEEE International Symposium on Circuits and Systems, 2005. ISCAS 2005, Vol. 1, May 2005.
[8] Malvar, H.S., Hallapuro, A., Karczewicz, M. and Kerofsky, L., “Low-complexity transform and quantization in H.264/AVC” , IEEE Transactions on Circuits and Systems for Video Technology, Volume 13, Issue 7, July 2003.
[9] GBjontegaart and K.Lollcvold, “Context-adaptive VLC (CAVLC) coding of coefficients” Doc. JVT-028, JVT of ISO MPEG & ITU VCEG, 3rd Meeting, Rairfax, Virginia, USA, May. 2002.
[10] Qiang Peng and Jin Jing, “H.264 codec system-on-chip design and verifivation”. Proceedings of 5th International Conference on ASIC, 2003, Volume: 2 , 21-24 Oct. 2003,Pages:922 -925 Vol.2
[11] Richardson, I. E.G., “H.264/MPEG-4 Part 10: Variable Length Coding,” A white paper. [Online]. Available: http://www.vcodex.com, October 2002
[12] Xilinx, “Virtex-II Platform FPGA User Guide”, UG002 (v1.4) 1 November 2002.
[13] Xilinx, “Platform Specification Format Reference Manual”, UG131 (v1.0) August 20, 2004.
[14] IainE. G. Richardson, H.264 and MPEG-4 Video Compression, 2003.
[15] Joint Video Team (JVT) of ISO/IEC MPEG&ITU-T VCEG,“ISO/IEC 14496-10”, 2003.
[16] Jung-Chau Jeng and Tian-Sheuan Chang, “Algorithm and Architecture Design for H.264/AVC Deblocking Filter and Intra Coding”. twins.ee.nctu.edu.tw, June 2005.