製程技術逐漸微縮至65奈米甚至45奈米，相同尺寸晶片的功能也越來越強大，使得電子產品訊號的傳輸量與電流頻率也隨之增加，訊號完整度(signal integrity)也因此大受影響，故對晶片做整合是個趨勢，晶片整合的方法大致有兩種，一是系統單晶片 (SOC System-On-a-Chip)，另外則是系統級封裝(SIP System-in-a-Package)。系統單晶片與系統級封裝上之金屬連接線的訊號傳遞是目前設計電路的主要瓶頸，主要是金屬連線(interconnect)產生寄生電阻(R)、寄生電感(L)與寄生電容(C)對整體電路有不良的影響，也因電流頻率的增加，以至於寄生電感變得越來越重要。

寄生參數電阻、電感與電容對於電路皆有其不良影響，電阻會產生RC delay、熱效應(thermal effect)與肌膚效應(skin effect)等效應，電容會產生RC delay與串音(cross talk)，而電感也會因串音造成訊號傳遞時的錯誤，這些寄生參數衍生的效應皆是電路設計者須重視不容忽略的問題。

綜合上述所說，因此正確抽取這些寄生參數對設計一個高速電路有相當大的影響。因為市面上的解電磁場軟體(field solver)的複雜輸入格式，令人難以使用，還會花不少時間於各種參數的抽取，另外就是市面上的 EDA軟體採集總模型(lumped model)，故本論文提出一個整合性高、速度快且能產生散佈式的電性模型軟體，來評估在半導體產業中必須考慮的信號完整性。在這套軟體內，我們針對四層印刷電路板與兩層印刷電路板設計出一些常見的金屬連線結構，建立相對應的電阻與電感的表格資料庫，利用這些金屬連線結構的組合來模擬真實電路中的金屬連線，並且開發一個令人親切好用的程式介面，設計者在程式介面上輸入金屬連線結構的參數後，除了會快速輸出該金屬連線的寄生參數電阻、電感與電容，還會產生設計者所要SPICE netlist和波形圖。

The technology of process is shortened to 65 nanometer, even to 45 nanometer. The functionalities of the same size chip is stronger and stronger. This cause increases of transmission and frequency of electronic products. Therefore, the signal integrity is also affected. So, the current trend is to integrate the chips. The methods of integration are SoC (System-On-a-Chip) and SiP (System-in-a-Package) generally. The bottleneck of SoC and SiP circuit designs are the signal propagation of interconnects. It is because that resistance, inductance and capacitance of interconnects have negative influences on whole circuits. Also, because of the increase of frequency, inductance becomes more and more important.

The resistance, inductance and capacitance have negative effects on circuits. Resistance will cause RC delay, thermal effect and skin effect. Capacitance will cause RC delay and cross talk, and the cross talk of inductance will also bring about false switch. These effects of parasitic parameters could not be neglected by circuit designers.

Due to the above reasons, correctly extracting the parasitic parameter plays an important role on designing a high speed electronic circuit. Generally we use field solver to get the parasitic parameters; however it is difficult to describe the input of field solver and time-consuming when we use the field solver. Due to the above mentioned reasons, this time we refer to a high integrity, fast, and bring the distributed model to evaluate the signal integrity when it comes to semi-conductor industry. In this software, we aim on 4-layer and 2-layer PCB to design some general interconnects and build responsive resistance and inductance’s data which uses the combination of the interconnects to simulate the metal wire connection in real circuit and design a user friendly graphical user interface. The designer can key in the parameters of the interconnects on the software interface and it will come out quickly to the responsive SPICE netlist and waveform.

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[2] K. Shih, “Electromagnetic Field Simulation Software Based Nanometer Resistance Analysis for Supporting Parametric Testing and SoC Designs” Master Degree Thesis, Hsinchu, Taiwan, October, 2006.

[3] T. Liu, “Accurate Nanometer Inductance Modeling for SoC Designs” Master Degree Thesis, Hsinchu, Taiwan, June, 2005.

[4] W.Chuang, “Accurate inductance modeling of various wirebonds for high-performance system-in-package designs” Master Degree Thesis, Hsinchu, Taiwan, June, 2005.

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