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研究生: 劉芸菲
Liu, Yun-Fei
論文名稱: 於多層單元之自旋轉移力矩隨機存取記憶體建立高能源效率之末級快取整合機制
Unifying Direct and Split Cache Designs on MLC STT-RAM Least-Level Cache for Energy Efficiency Boost
指導教授: 石維寬
Shih, Wei-Kuan
口試委員: 張原豪
Chang, Yuan-Hao
鍾偉和
Chung, Wei-Ho
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 資訊系統與應用研究所
Institute of Information Systems and Applications
論文出版年: 2019
畢業學年度: 107
語文別: 英文
論文頁數: 26
中文關鍵詞: 快取自旋轉移力矩隨機存取記憶體多層單元末級快取
外文關鍵詞: Cache, STT-RAM, MLC, LastLevelCache
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  • 在現代世界中,我們應該通過將材料變為非揮發性類型來管理能量,因為電池壽命有限。有很多關於多層單元自旋轉移力矩隨機存取記憶體管理的作品,但也基於相同的映射思想,它將多層單元結構的一個單元內的位分開。 在我們的工作中引入了另一種緩存策略,它將直接映射和單元分割映射結合在一起,以提高能效。除了訪問主存儲器的成本之外的結果表明我們減少了高達30%的能量和21%的延遲。


    In the modern world, we should manage the energy as well as we could by changing the material into non-volatile type since battery life is limited. There are many works about MLC STT-RAM management but also based on the same mapping idea which is split the bit inside one cell of MLC structure. In our work introduce another cache strategy which combines direct mapping and cell split mapping together for better energy efficiency. And the result which except the cost of accessing main memory shows that we reduce up to 30% energy and 21% latency.

    1. Introduction 3 2. Background and Motivations 5 2.1 Background 5 2.1.1 MLC STT-RAM 5 2.1.2 Exclusive Cache Structure 6 2.2 Motivation 7 3. Our Method 9 3.1 Overview 9 3.2 Design Detail 10 3.2.1 Cross Cache Structure 10 3.2.2 Counter-based Hot Chunk Identification 11 3.2.3 The Empty Policy 12 4. Performance Evaluation 15 4.1 Experimental Setup 15 4.2 Experimental Result 17 4.3 Argument Exploration 20 5. Conclusion 23 6. References 24

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