隨著半導體製程的萎縮和時間量化技術的進步，時間量測的解析度越來越高，同時，因著製程變異而產生的不線性現象也變得更顯著。
本篇論文改良了用於時脈抖動量測的脈衝萎縮型(pulse-shrinking-based)時間量化器(Time-to-Digital Converter, TDC)，支援了晶片內特性分析以及不線性問題的校正。我們使用了 (1) 單向變容細胞(One-Way Varactor Cells, OWVCs)來做刻度校正 (2) 標準細胞元件之全數位式非整數型鎖相迴路提供訓練時脈訊號 (3) 精密的校正演算法去使各個刻度趨於一致。使用這些技術可以在晶片上得到該時間量化器的特性分析，也可以透過校正達到容忍製程變異的效果。
本篇論文使用了90nm CMOS製程的標準細胞元件。在經過校正後，時間量化器的微分非線性度(Differential Nonlinearity, DNL)和積分非線性度(Integral Nonlinearity, INL)分別減少了45%及84%，測量誤差從7.03皮秒降至1.28皮秒。

As the scale shrinking in the semiconductor manufacturing processes and time quantization techniques develop, the resolution of timing measurement is becoming higher. At the same time, the nonlinear effects caused by process variations are also growing significantly.
This thesis proposes a pulse-shrinking-based Time-to-Digital Converter (TDC) for clock jitter measurement with on-chip characterization and calibrating methodology for the nonlinearity issue. We achieve our goal by using (1) One-Way Varactor Cells (OWVCs) for the resolution tuning, (2) a cell-based Fractional-N All-Digital Phase-Locked Loop (ADPLL) for the precise training clocks, and (3) a sophisticated algorithm that will guide the tuning cells to make the resolutions more consistent. By using these techniques, we can obtain the TDC’s on-chip characteristics and achieve process variation resilience.
In this thesis, we use 90nm CMOS process standard cells for implementation. With this calibration methodology, the TDC’s Differential Nonlinearity (DNL) and Integral Nonlinearity (INL) are reduced by 45% and 84% respectively. The measurement error is reduced from 7.03ps to 1.28ps.

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