以改善良率及可靠性為目標之有效率的冗餘接點安插方法

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研究生：	李光曜 Lee, Kuang-Yao
論文名稱：	以改善良率及可靠性為目標之有效率的冗餘接點安插方法 Efficient Approaches to Redundant Via Insertion for Yield and Reliability Improvement
指導教授：	王廷基 Wang, Ting-Chi
口試委員:
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 資訊工程學系 Computer Science
論文出版年：	2009
畢業學年度：	97
語文別：	英文
論文頁數：	138
中文關鍵詞：	冗餘接點、接點密度、零壹整數線性歸劃、實體設計、設計自動化
外文關鍵詞：	redundant via, via density, 0-1 integer linear program, physical design, electronic design automation
相關次數：	點閱：1 下載：0
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In an IC layout, a via provides a connection between two net
segments from adjacent metal layers. Due to various reasons such as cut misalignment, line-end shortening, and voiding effect induced by electromigration and thermal stress, a via may fail partially or completely. As a result, to reduce the yield loss due to via failures is one of the most important issues in design for manufacturability.

A well known and highly recommended method to improve via yield is to add a redundant via adjacent to a single via, enabling a single via failure to be tolerated. Therefore, redundant vias can improve the reliability of a design. Moreover, for each region of a pre-defined size on a via layer, its via density can be defined as the number of vias within it. If too many redundant vias are inserted into a region, and the amount exceeds the maximum via density constraint, the pattern distortion of the vias in that region will become serious and hence the yield/reliability of the design will become worse. Therefore, after inserting redundant vias into a design, the maximum via density rule should be re-verified.

In this dissertation, we investigate several redundant via insertion problems for yield and reliability improvement in a post-routing stage. We first study the classical post-routing redundant via insertion problem. We formulate it as a maximum independent set (MIS) problem and present an efficient graph construction algorithm to model the problem. Moreover, we present an efficient heuristic
and a 0-1 integer linear program (0-1 ILP) based optimal approach to solve this problem. Since redundant vias can be classified into on-track and off-track ones, and on-track ones use less routing resources and have better electrical properties, we also study the problem of redundant via insertion with a preference for on-track redundant vias. We present two heuristic methods to increase the amount of on-track redundant vias. We also present a 0-1 ILP based
approach to optimally solve this problem. Next, we investigate the problem of redundant via insertion with via density consideration and propose a two-stage heuristic and a 0-1 ILP based optimal approach. We also study how to simultaneously consider the via density and the preference for on-track redundant vias and propose several heuristics and a 0-1 ILP based optimal approach. Finally, we study how to utilize a wire bending technique to improve the insertion rate of redundant vias and propose an efficient and effective 0-1 ILP based solution. We also extend the 0-1 ILP approach to consider the via density and/or the preference for on-track redundant vias.

Each of our redundant via insertion approaches mentioned above has been implemented and its robustness is well demonstrated by experiments on real circuits.

在IC 設計中，接點(via)所扮演的功能為替相鄰兩層的金屬線段提供訊號通
路。然而，由於在晶片生產過程中的接點失準(cut misalignment)、金屬線之線
端點內縮(line-end shortening)及因電致遷移(electro-migration)或熱應力
(thermal stress)效應所造成之空孔(void)缺陷等因素，可能造成部分或整個接
點毀損。因此，如何降低因接點毀損所造成的良率下降則為可製造性導向之設計
方法(design for manufacturability)中重要議題之一。
加入一冗餘接點(redundant via)到各個接點旁為一廣為人知且較為推薦的
方法。對於每個被加入冗餘接點的接點處，由於同時存在兩個接點，當單一個接
點損毀時並不會對晶片的功能性造成影響；也因此晶片的良率及可靠度可望獲得
提升。此外，對於每個接點層(via layer)上的區域(region)，其接點密度(via
density)可被定義為其所包含的接點個數。若過多的接點被安插到某區域中，而
違反了最大接點密度限制，則接點形狀扭曲(pattern distortion)的現象將變得
更為嚴重，反而造成晶片良率及可靠度下降。因此在進行冗餘接點安插後，接點
密度必須被再次驗證。
在這篇論文中我們研究許多以改善良率及可靠度為目標之後繞線階段
(post-routing)冗餘接點安插問題。最初，我們研究傳統的後繞線階段冗餘接點
安插問題。我們將其轉換為一最大獨立子集(maximum independent set)問題，
並提出一有效率的圖形建構演算法。此外，我們更提出一有效率的啟發式方法
(heuristic)及一個以零壹整數線性規劃(0-1 integer linear program)為基礎
的方法來解決此問題。因為冗餘接點可被分類為在軌冗餘接點(on-track
redundant via)及離軌冗餘接點(off-track redundant via)，且在軌冗餘接點
具備較佳的電氣特性，我們亦研究一個具在軌接點偏好的冗餘接點安插問題。我
們提出兩個啟發式方法來增加所安插的在軌冗餘接點數量並提出一個以零壹整
數線性規劃為基礎的最佳化方法。接著我們研究具接點密度考量之後繞線階段冗
餘接點安插問題。我們亦研究如何同時考量在軌接點偏好及接點密度並提出許多
啟發式方法及一個以零壹整數線性規劃為基礎的最佳化方法。最後，我們研究如
何利用線段彎曲(wire bending)技術來增進冗餘接點安插率並提出一個快速又有
效的以零壹整數線性規劃為基礎的最佳化方法。我們亦擴充此方法使其能考慮在
軌接點偏好及/或接點密度。
上述所提出的每個方法都已被實作且其強健性(robustness)皆已藉由應用
於實際晶片上所呈現。

Overview 1
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Dissertation overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Heuristic Methods for Double Via Insertion 6
1 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2 Double vias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 Problem formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Maximum bipartite matching formulation . . . . . . . . . . . . . . 10
2.2 Maximum independent set formulation . . . . . . . . . . . . . . . . 11
3 Confict graph construction . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 A heuristic for solving the MIS problem . . . . . . . . . . . . . . . . . . . . 16
5 Extensions to other double via insertion problems . . . . . . . . . . . . . . 18
5.1 Via density consideration . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.1 Via density rules and problem denition . . . . . . . . . . 19
5.1.2 Overview of our two-stage heuristic . . . . . . . . . . . . . 21
5.1.3 Via density calculation . . . . . . . . . . . . . . . . . . . . 21
5.1.4 Redundant via removal . . . . . . . . . . . . . . . . . . . . 24
5.2 On-track preference . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.3 Simultaneous consideration of via density and on-track preference . 28
6 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.1 Results on the DVI problem . . . . . . . . . . . . . . . . . . . . . . 31
6.2 Results on the DVI/VD problem . . . . . . . . . . . . . . . . . . . 32
6.3 Results on the DVI/ON problem . . . . . . . . . . . . . . . . . . . 36
6.4 Results on the DVI/ON+VD problem . . . . . . . . . . . . . . . . 36
7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Optimal Solutions to Double Via Insertion 41
1 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2 0-1 ILP formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3 Speed-up methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1 Reducing the number of constraints . . . . . . . . . . . . . . . . . . 43
3.2 Pre-selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
3.3 Computing connected components . . . . . . . . . . . . . . . . . . . 49
4 An eficient ILP-based approach . . . . . . . . . . . . . . . . . . . . . . . . 51
5 Extensions to other double via insertion problems . . . . . . . . . . . . . . 52
5.1 Via density consideration . . . . . . . . . . . . . . . . . . . . . . . . 52
5.2 On-track preference . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.3 Simultaneous consideration of via density and on-track preference . 58
6 An MWBM based approach for a constrained
DVI/ON problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
7 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
7.1 The completeness of 0-1 ILP formulation . . . . . . . . . . . . . . . 62
7.2 Results on the DVI problem . . . . . . . . . . . . . . . . . . . . . . 66
7.3 Results on the DVI/VD problem . . . . . . . . . . . . . . . . . . . 72
7.4 Results on the DVI/ON problem . . . . . . . . . . . . . . . . . . . 76
7.5 Results on the DVI/ON+VD problem . . . . . . . . . . . . . . . . 80
7.6 Results on the CDVI/ON problem . . . . . . . . . . . . . . . . . . 83
8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Enhanced Double Via Insertion Using Wire Bending 87
1 Problem definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
1.1 Wire bending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
1.2 The DVI/WB problem . . . . . . . . . . . . . . . . . . . . . . . . . 89
2 Enhanced conflict graph . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
3 Graph construction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3.1 Wire bending for double via insertion . . . . . . . . . . . . . . . . . 92
3.2 An algorithm to construct an enhanced conflict graph . . . . . . . . 96
4 0-1 ILP formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5 An efficient ILP-based approach . . . . . . . . . . . . . . . . . . . . . . . . 101
6 Extensions to the problem of simultaneous double via insertion and wire
bending . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1 Via density consideration . . . . . . . . . . . . . . . . . . . . . . . . 105
6.2 On-track preference . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.3 Simultaneous consideration of via density and on-track preference . 111
7 Experimental results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
7.1 Graph construction with and without wire bending . . . . . . . . . 113
7.2 Results on the DVI/WB problem . . . . . . . . . . . . . . . . . . . 113
7.3 Results on the DVI/WB+VD problem . . . . . . . . . . . . . . . . 119
7.4 Results on the DVI/WB+ON problem . . . . . . . . . . . . . . . . 123
7.5 Results on the DVI/WB+ON+VD problem . . . . . . . . . . . . . 126
8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Conclusions 130
1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
2 Future works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

                                

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