伴隨著半導體製程技術的演進，記憶體的容量以及密度的迅速成長，使得在可靠度(Reliability)的維持變成一個很重要的考量因素。而錯誤檢測與糾正 (Error Detection and Correction, EDAC) 技巧又是常被用來增進記憶體晶片可靠度上的解決方法。它能有效地保護記憶體免於遭受軟錯誤 (Soft Error)的影響；進而提高其可靠度，同時保有資料修復的完整性。然而由於在傳統錯誤檢測與糾正的作法，我們無法滿足記憶體擁有較長的位元組需求。再者，記憶體晶片在功率消耗上也被視為是另一項重大的評估。我們可以藉由減少頻率更新的方式來降低功率消耗，不過資料完整性必須被審慎考量。
因此，就上述觀點而言，錯誤更正碼的編碼方式變成是一個焦點的所在。在本篇論文中，我們提出一個適用於低功率記憶體的錯誤更正碼之奇偶校驗檢查矩陣產生器設計。透過自動化的過程，使用者能夠依據記憶體的規格，支援不同的編碼長度，產生相對應適當的奇偶校驗檢查矩陣。另外，由於編碼方式是透過數個記憶體讀寫單位的位元結合組成一組完整的位元組，不過就目前記憶體讀寫方式尚以單一記憶體讀寫位元為單位，所以我們將資訊位元組部分利用數個位元當作某一個記憶體讀寫單位的辨別作排列，也就是而本篇文章所提出來的方法。其所需的校驗位元數目相較於傳統上運用於單錯誤更正－雙錯誤偵測能力的錯誤更正碼，擁有較少的校驗位元數目。同時從實驗結果得知，就可容忍的範圍內，此方法可維持其錯誤更正碼機制的可行性。

With the feature size of semiconductor technology continues to reduce, how to keep a high level of reliability for memory products has become an important issue. Specifically, Error Detection and Correction (EDAC) techniques are commonly used in this scheme. It protects against soft errors and thereby enhances system reliability and data integrity. However, the conventional EDAC techniques would not be satisfied with memories with long codewords. Moreover, power reduction in memories like cells can be always done by keeping refreshing the frequency, but the data integrity should be considered with carefully.

On account of the above issues, we propose an EDAC scheme for designing the parity check matrices which can be used on memories with different sizes of long codewords. The parity check matrix generator proposed in the paper can apply memories to reduce refreshing power consumption in single-error correcting, double error-detecting codes (SEC-DED). Power is minimized with little or no impact on area and delay, using degree freedom in selecting the parity check matrix of the error correcting code. It presents codes that use a smaller number of circuits and requires a shorter gate delay time than known codes. The overall construction methods are useful for systematic constructing the parity check matrices.

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