渦輪碼(Turbo Code)可以達到接近理論的通道容量，也已經成為下一代行動電話的標準。對於可攜式平台而言，降低功率消耗是非常重要的。
本論文著重於低功率SOVA渦輪碼解碼器的演算法以及其在超大型積體電路上的實現。SOVA演算法比MAP演算法簡單且更適合於積體電路的實現，不過效能會降低一些。

兩段式SOVA(two-step SOVA)先使用Viterbi演算法找出近似於最後的存活路徑(survivor path)，然後再進行更新extrinsic值的動作，由於在每一時刻只要追蹤兩條路徑---存活路徑及競爭路徑(competing path)，因此，複雜度可以大大地減低。另外，我們運用SST重新編碼，在訊號雜訊比不錯的情況下，存活路徑大部份會通過zero state，使得追蹤單元內狀態的變化減到最低。因此，功率的消耗可以減少。

由於反覆解碼的特性，一個小電路可以判斷出是否可以停止解碼的動作，停止解碼的條件為全部的extrinsic值與解碼後的訊號之正負號完全一樣。模擬的結果，在訊號雜訊比為3dB及最大的iteration次數為6時，可以省下百分之六十的動作。一個低功率的ACS單元可以節省一個加法器，而且加法或減法運算所使用的位元寬度變小，因此也可以降低功率的消耗。另外，我們提出兩個方法—gated clock 及two-phase clock 進一步地改善追蹤單元的功率。

最後，我們利用Verilog硬體描述語言描述我們的架構，並且使用Synopsys Design Compiler進行邏輯合成，由Synopsys Power Compiler 估計的結果,可以省下百分之12.1的功率。

Turbo code can approach the theoretical channel capacity and has been regarded as the standard in the next generation mobile phones. For portable platforms, power consumption is very critical.
In this thesis, we focus on the algorithm and VLSI implementation of the low-power SOVA-based Turbo code decoder. SOVA is simpler and more appropriate than MAP for VLSI implementation with a little degradation.

A low complexity SOVA (Two-Step SOVA) which precedes VA to find the “almost” final survivor path and then performs the updating operations can reduce the hardware complexity. In order to minimize the state transition for Viterbi decoders, SST (Scarce State Transition) scheme was proposed. It can be easily extended to SOVA decoder.

Due to the characteristic of iterative decoding, a termination criterion can be evaluated with a simple additional circuit. Simulation shows 60% iterations can be saved at SNR=3.0dB(if the number of iteration is 6). A low power ACSU (Add-Compare-Select Unit) which saves one adder also lowers the power consumption. We propose two schemes—gated clock and two-phase clock, to further improve the power consumption of the trace-back units.

Finally, the design of Turbo code decoder is described with Verilog HDL code and synthesized with Synopsys Design Compiler. The power was estimated with Synopsys Power Compiler. From the simulation, 12.1% power can be saved.

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