晶片網路的設計與效能評估｜國立清華大學博碩士論文庫

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研究生：	林倬安 Jwo-An Lin
論文名稱：	晶片網路的設計與效能評估 Design and Performance Evaluation of on-chip Interconnection Network
指導教授：	許雅三 Yarsun Hsu
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2007
畢業學年度：	95
語文別：	英文
論文頁數：	102
中文關鍵詞：	晶片網路、實體網路管理方案
外文關鍵詞：	Network on Chip, Physical Channel Management Scheme
相關次數：	點閱：3 下載：0
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隨著晶片製程的發展，單一晶片上所能夠容納的功能元件日益增多，晶片的設計重點也從原本的增進各個功能元件效能，變成如何讓各個功能元件有效率的合作來解決一個龐大的問題。在這種情況之下，一個高效率的連接系統是必須的。然而，過去常使用的全域分享匯流排（global shared medium bus），以及區段匯流排（segmented bus），基於其以匯流排為主（bus centric）的特性，會遭遇到很多問題，最嚴重的包括網路擴充性嚴重受限，以及深微米的連線效應。因此，晶片網路（network on chip）的設計就逐漸發展，且為眾人所接受。

在本篇論文當中，我們將探討有關晶片網路的設計以及其效能評估。首先，我們會針對晶片網路中的必要元件，也就是網路儲存器，作一個最佳化，再來，基於這一個最佳化的結果，我們會開始建立不同網路拓樸的網路，並分別對這些網路中的網路節點作調整，在符合晶片設計限制的情況之下，提升整體網路的效能。然後，我們會提出實體網路資源管理方案，依據執行過程中的交通狀態，來動態調整實體網路資源的分配。

接下來，為了驗證我們所提出的各種概念及網路設計可以正確的工作，我們建立一個網路模擬平台，這個平台是以 SystemC語言建立而成，該語言支援C的函式庫，並且可以用週期準確的方法描述硬體電路，方便我們作有效且快速的網路效能評估。

在確認模擬平台是正確可靠之後，我們利用這個模擬平台，作許多相關的網路評估。包含：環形拓樸網路的評估；基於不同拓樸的網路評估；不同儲存器容量對不同拓樸網路所造成的影響；規則與不規則交通狀態對不同拓樸網路所造成的影響。這些評估的結果，提供了我們在晶片網路設計上的概念方向以及進一步網路效能提升設計的參考。

With the improvement of chip manufacture process, a single chip may contain more and more functional units. The chip design concepts have emphasized more on the co-operation of a single chip than the improvement of each functional unit. For these reasons, a high efficient interconnection is necessary.

In the past few years, the most frequently used interconnection is global shared medium bus. However, the efficiency of this method is very poor and the deep sub-micron wiring effect is very severe. In order to improve the interconnection efficiency, pipelined bus and segmented bus were proposed. These methods can further improve the interconnection efficiency; however, their performances are severely limited by the bus centric feature. For these reasons, a network on chip (NoC) design concept was proposed.

In this thesis, we are going to discuss the design of on chip interconnection network and their performance evaluation. First, we propose a new network buffer design concept, which eliminates the cycle delay due to state switching. By adopting this buffer architecture, we build up three different types of networks based on three different network topologies. These networks can support multiple data transfers simultaneously. We also optimize the network nodes in each network to further improve the network performance and reduce the extra cost on both hardware complexity and intra-node wirings. In addition, we propose a physical channel resource management scheme and prove that it is a good solution for multiple virtual channels to share one physical channel resource.

After designing the networks, we build up a simulation environment based on SystemC, which can describe the detailed behavior of each network component in cycle accurate RTL level, and support fast network performance evaluations. Using this network simulation environment, we have done lots of network evaluations, which show the design tradeoffs between hardware cost and network performance in different situations. This information provides a guideline in NoC design, and is very useful for further performance improvements.

Chapter1 Introduction    1
1 The development of NoC    1
2 Motivation and objective    3
3 Thesis organization    4
Chapter 2 Background    6
1 Message layer protocol    6
2 Network topology    8
3 Switching methods    9
3.1 Circuit switching    9
3.2 Packet switching    10
3.3 Wormhole switching    12
4 Routing algorithms    14
5 Network anomalies    15
5.1 Deadlock anomaly and its solution    15
5.2 Livelock anomaly and its solution    18
5.3 Starvation anomaly and its solution    18
6 Physical layer implementation    18
Chapter 3 On-Chip Interconnection Network Design – based on the optimization of network buffers and the physical channel management scheme    21
1 Buffer design optimization    22
1.1 Traditional one port FIFO    22
1.2 Improved two ports FIFO    23
1.3 New FIFO design for network on Chip    24
2 Build up a network in ring topology    27
2.1 Physical links and buffers allocation in a ring network    27
2.2 Design a network node in a ring network    28
2.3 Routing algorithms in a ring network    34
2.4 Arbiter design issues in a ring network    34
2.5 Anomalies prevention in a ring network    35
3 Build up a network in 3X3 torus topology    36
3.1 Physical links and buffers allocation in a 3X3 torus network    36
3.2 Design a network node in a 3X3 torus network    37
3.3 Routing algorithms in a 3X3 torus network    40
3.4 Arbiter design issues in a 3X3 torus network    40
3.5 Anomalies prevention in a 3X3 torus network    41
4 Build up a Network in 3X3 mesh Topology    41
4.1 Physical links and Buffer allocation in a 3X3 mesh network    41
4.2 Design a network node in a 3X3 mesh network    42
4.3 Routing algorithms in a 3X3 mesh network    42
4.4 Arbiter design issues in a 3X3 mesh network    44
4.5 Anomalies prevention in a 3X3 mesh network    44
5 Physical channel management scheme    44
Chapter 4    Simulation Results and Analysis    51
1 Simulation Environment    51
2 Performance matrix definitions    53
3 Standard performance result formats    55
3.1 Chaos Normal Form (CNF)    55
3.2 Burton Normal Form (BNF)    56
4 Performance evaluation in ring topology networks    57
4.1 Performance comparisons between two ring topology networks adopting different buffer architectures.    57
4.2 The relation between average flit latency and flit traveling distance in a ring topology network    62
4.3 Network performance evaluation between the ring topology networks with different numbers of nodes    63
4.4 Network performance evaluation between the ring topology networks with different numbers of physical rings    65
5 Comparison between different networks with different topologies    68
5.1 Estimate the hardware cost between ring, 3X3 torus and 3X3 mesh network    68
5.2 Network performance between different networks with different topologies    69
6 The Influence of Network Buffer Size in Different Networks    72
6.1 Ring Topology Network with 9 Network Nodes    72
6.2 3X3 Torus Topology Network with 9 Network Nodes    76
6.3 3X3 Mesh topology with 9 network nodes    79
7 Performance evaluation between uniform traffic and non-uniform traffic in different networks    83
7.1 Performance evaluation between uniform traffic and non-uniform traffic in ring topology network    83
7.2 Performance evaluation between uniform traffic and non-uniform traffic in 3X3 torus topology network    85
7.3 Performance evaluation between uniform traffic and non-uniform traffic in 3X3 mesh topology network    87
8 Performance evaluation between different networks adopting different methods to realize multiple virtual channels across one physical channel    89
Chapter 5    Conclusions and Future Works    98
1 Conclusions    98
2 Future works    99
References    101

                                

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