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研究生: 許震緯
Hsu, Chen-Wei
論文名稱: PowerDepot: 超快速系統階層之晶片設計功耗估算方法
PowerDepot: Superfast System-Level Power Estimation Methodology for IC's
指導教授: 黃錫瑜
Huang, Shi-Yu
口試委員:
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2009
畢業學年度: 98
語文別: 英文
論文頁數: 62
中文關鍵詞: 電子系統階層功率估算SystemC
外文關鍵詞: Electronic System Level, power estimation, SystemC
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  • 系統層級之設計其複雜度不斷地增加使得設計趨勢逐漸由暫存器級 (Register-Transfer Level) 移往電子系統級 (Electronic System Level),SystemC 是目前最重要的電子系統級語言之一,在SystemC之系統設計流程中常導入抽象層級 (Abstraction Level) 的觀念,應用不同的抽象層級可以簡化設計之複雜度進而縮短系統模擬之時間,但它並不支援功耗之估算。由於功耗估算是系統設計中的一項關鍵,在這篇論文中,我們提出一個電子系統級之功耗估算軟體PowerDepot來加強SystemC,使其擁有功耗估算之能力。
    PowerDepot是由C++撰寫而成,因而適用於各種以SystemC為其基礎之電子系統級平台。在電子系統級進行功耗估算需借助功率模型,但將功率模型嵌入電子系統級平台時,常遇到由電子系統級和其他抽象層級之間差異造成的抽象性 (Abstraction)、能見度 (Observability) 和對應性 (Mapping) 之問題。因此,嵌入之過程常需要對原本之系統電子級模組之函數進行修改,但此過程常需要手動進行而且容易造成錯誤。在系統中之不同模組其功耗可以分為兩類,第一類之功耗來源為模組內部之運算造成,第二類之功耗主要與其在匯流排上之操作有關,PowerDepot可快速將適用於矽智材內 (In-IP) 或匯流排上 (On-Bus) 之功率模型嵌入電子系統級平台,矽智材內之功率模型將以巨集 (Macro) 方式嵌入系統,而匯流排上之功率模型則連接到所要監測的埠 (Port),此移植功耗模型之方式將盡可能地降低對電子系統級平台之侵入,我們的方法應用在PAC Duo之電子系統級平台上所得到之誤差約為2%,而此電子系統級的功耗估算還能應用在系統架構之分析上。


    The rapidly increasing complexity of the system-level design makes the design trend shifting from the RTL to the ESL. SystemC is one of the most important languages at ESL. However, SystemC does not support the power estimation which is a critical issue for the system-level design. In this paper, we present our ESL power estimation tool, called PowerDepot, which enhances SystemC with the capability for power estimation. The power models must be used in order to perform power estimation at ESL. However, embedding the power models into the ESL platform often encounters the abstraction, observability, and mapping issues which are introduced by the gap between ESL and other abstraction levels. The embedding procedure requiring the modifications to the original functions of the ESL modules is not only error-prone but also tedious. PowerDepot provides a solution which utilizes the pre-defined macros for the quick insertion of power models. We apply our methodology on the PAC Duo ESL platform, and the average error of the results is less than 2% with small simulation overhead. Besides, the results could be analyzed for architecture analysis.

    Abstract(English) i Abstract(Chinese) ii Acknowledgement(Chinese) iii Content iv List of Figures i List of Tables i Chapter 1 Introduction 1 1.1 Motivation 3 1.2 Thesis Organization 4 Chapter 2 Background 5 2.1 Overview of SystemC 5 2.1.1 System Design Methodologies 6 2.1.2 SystemC Language Architecture 8 2.1.3 Abstraction Level of SystemC 10 2.1.4 System Model of SystemC 15 2.1.5 Simulation Flow of SystemC 17 2.2 Related Work 21 2.3 Challenges of ESL Power Estimation 23 Chapter 3 Usage Flow of PowerDepot 25 3.1 Monitor Generation 26 3.1.1 In-IP Power Monitor 29 3.1.2 On-Bus Power Monitor 32 3.2 Monitor Insertion 35 3.2.1 Discussion of Abstraction Level and Power Monitor 37 3.3 ESL Re-Simulation 39 Chapter 4 Implementation of PowerDepot 40 4.1 Components of PowerDepot 40 4.2 Construction of Hierarchy 41 4.3 Energy Calculation 43 Chapter 5 Experimental Results 46 5.1 Simulation Platform 46 5.2 Simulation Overhead 48 5.3 Experimental Results of AXI System of PAC Duo 49 5.4 Experimental Results of Different Cache Sizes 53 5.5 Experimental Results of Different Cores 56 Chapter 6 Conclusions 59 Bibliography 60

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