研究生: |
王勝弘 Wang, Sheng-Hong |
---|---|
論文名稱: |
矽離子佈植改善4H-SiC氧化製程之實驗 Experimental Study of 4H-SiC Oxidation Process with Si Implantation |
指導教授: |
黃智方
Huang, Chih-Fang |
口試委員: |
崔秉鉞
Tsui, Bing-Yue 吳添立 Wu, Tian-Li |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2018 |
畢業學年度: | 106 |
語文別: | 中文 |
論文頁數: | 51 |
中文關鍵詞: | 碳化矽 、氧化製程 、電子遷移率 、離子佈植 |
外文關鍵詞: | 4H-SiC, ThermalOxidation, ChannelMobility, Implantation |
相關次數: | 點閱:2 下載:0 |
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碳化矽金氧半場效電晶體的場效電子遷移率過低(5~10cm^2/V∙s)一直是碳化矽元件最大的缺點,近年來已經發展出使用氧化後一氧化氮熱退火可以讓電子遷移率有效提升至約30cm^2/V∙s,而本論文提出在氧化製程前進行矽離子佈植的方式來改善氧化層品質,希望藉此開創出新的提升場效電子遷移率的方法。
論文中我們在氧化前先進行一次低能量、低劑量的矽離子佈植,不經過離子佈植後退火,接著在1150℃、乾氧環境下持續6小時閘極氧化製程,不進行一氧化氮熱退火,製作碳化矽金氧半場效電晶體與金氧半電容,並以純乾氧的標準閘極氧化製程作為實驗對照組,實驗結果發現經過氧化前矽離子佈植試片其電子遷移率由6.38cm^2/V∙s提升至7.59cm^2/V∙s。藉由電荷汲引方式量測得知平均表面缺陷密度也由4.079×10^12 eV^(-1) cm^(-2)下降到3.764×10^12 eV^(-1) cm^(-2),且沒有閾值電壓飄移的問題。
Low field effect mobility (5~10 cm^2/V∙s) is one of the main challenges of SiC MOSFETs. Post-oxidation annealing in NO has been developed to enhance the mobility to about 30cm^2/V∙s in previous studies. In this study, silicon ion implantation before thermal oxidation is proposed as a novel method to improve the channel mobility of SiC MOSFETs.
The silicon ion implantation process applied in this study is of low energy and low dose, without post-implantation annealing. This implantation process is followed by a gate oxidation in dry O2 at 1150℃ for 6 hours, without NO annealing. Compared to the control sample without pre-oxidation implantation process, the field effect mobility is increased from 6.38cm^2/V∙s to 7.59cm^2/V∙s, and the interface trap density is reduced from 4.079×10^12 eV^(-1) cm^(-2) to 3.764×10^12 eV^(-1) cm^(-2) from charge pumping measurements. In the meantime, no additional threshold voltage shift is caused by the new process.
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