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研究生: 湯松年
Tang, Song-Nien
論文名稱: 適用於無線個人/區域/都會網路應用之多模式快速傅立葉處理器設計
Design of the Multimode FFT Processors for WPAN/WLAN/WMAN Applications
指導教授: 張慶元
Chang, Tsin-Yuan
口試委員: 袁正泰
黃家齊
謝明得
馬席彬
黃元豪
學位類別: 博士
Doctor
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2011
畢業學年度: 100
語文別: 英文
論文頁數: 76
中文關鍵詞: 傅立葉轉換
相關次數: 點閱:4下載:0
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  • 隨著無線數據通訊的需求,無線區域網路(Wireless Local Area Network; 簡稱
    WLAN),無線都會網路(Wireless Metropolitan Area Network; 簡稱WMAN)以及無線個
    人網路(Wireless Personal Area Network; 簡稱WPAN)已被廣泛地開發並應用在系統平台
    上。針對此三種無線網路,相關的標準也在近期被提出,其中主要包括了IEEE 802.11n(因
    應WLAN),IEEE 802.11e/m(因應WMAN)以及IEEE 802.15.3a/c(因應WPAN)。在上述
    三種網路系統的實體層設計裡, 正交分頻多工(Orthogonal Frequency Division
    Multiplexing; 簡稱OFDM)是其主要的核心技術,而傅立葉轉換(Fast Fourier Transform;
    簡稱FFT)器則是OFDM 系統所需用的關鍵性零組件。
    從系統整合的觀點來看,為了可彈性地根據速度需求與所處環境來進行無線數據的
    擷取,一個擁有多模式(Multimode)傅立葉轉換器的三重無線個人/區域/都會網路系統是
    具有開發上的實用性。因此在本篇論文中,我們以傅立葉轉換硬體的兩種主要方案,即
    管線式(pipelined)和基於記憶體式(memory-based)的架構為基礎,提出適用於三重無線個
    人/區域/都會網路應用的多模式傅立葉轉換器設計。在管線式傅立葉轉換器的架構上,我們首先針對無線個人網路應用,以多路徑延遲
    迴授(multipath delay feedback; 簡稱MDF)結構作基礎,提出一個具有高輸出入率
    (throughput rate)之2048 點的傅立葉轉換器。藉由所提出之新穎的乘法化簡以及多路徑
    數值縮放(multidata scaling)方法,我們可在所呈現的架構中改善硬體效能。此外,為了
    進一步達到記憶體相關的節能,我們也在本篇論文中提到混合式記憶體擷取調度
    (mixed-memory-access-scheduling; MMAS)的方案。針對多模式運作的需求,我們也進階
    提出了一個靈活基數組態(flexible-radix-configuration; FRC)的MDF 架構。該架構能針對
    無線個人/區域/都會網路的應用,以有效益的硬體方式來執行相關的高輸出入率和可變
    點數並多重串數的傅立葉轉換運算。基於所提出的FRCMDF 結構,一個雙重最佳化
    (dual-optimized)的乘法方案也被陳明以進一步改善面積與功率的效益。此外,我們所提
    出的組態方式可針對跨模式下的功率可延展性(power scalability)提供了架構性的支援。
    除了根源於MDF 架構的作法,基於記憶體式(memory-based)的傅立葉轉換器架構
    也同樣被考量來針對無線區域網路,無線都會網路以及超寬頻(Ultra Wideband; UWB;
    即WPAN 系統的早期規格)的應用作多模式傅立葉轉換器的開發。在本篇論文中,我們
    亦提出一個基於記憶體式之多模式快速傅立葉處理器。該處理器可藉由新穎的記憶體配
    置方法連同一個節能的多模式傅立葉轉換核心,來有效率地執行無線區域/都會/超寬頻
    網路相關的傅立葉轉換運算。


    Chapter 1 Introduction -------------------------------------------------------------------------------1- 1.1 System Specification ------------------------------------------------------------------------ 1- 1.2 Review of FFT Hardware Architecture --------------------------------------------------- 3- 1.3 Motivation ------------------------------------------------------------------------------------ 6- 1.4 Thesis Organization ------------------------------------------------------------------------- 7- Chapter 2 Design Considerations ------------------------------------------------------------------ 8- 2.1 Design Considerations for the MDF-based approach ---------------------------------- 8- 2.1.1 Multipath Multiplication Mechanism ---------------------------------------------- 8- 2.1.2 Energy-Efficiency for Memory Access -------------------------------------------- 9- 2.1.3 Hardware Costs due to Increased Wordlengths ---------------------------------- 9- 2.1.4 Multimode Operations Mechanism ----------------------------------------------- 10- 2.2 Design Considerations for the Memory-based Approach --------------------------- 11- 2.2.1 High-capacity Multibank Memory Allocation ---------------------------------- 12- 2.2.2 Energy-efficient Multimode FFT Kernel ---------------------------------------- 14- Chapter 3 FFT Algorithm -------------------------------------------------------------------------- 15- 3.1 Radix-24/25 Algorithm for 512-point FFT --------------------------------------------- 15- 3.2 Flexible-radix Algorithm for Variable-length FFTs ---------------------------------- 17- 3.3 Extended Algorithm ----------------------------------------------------------------------- 18- Chapter 4 The Proposed MDF-based FFT Processor ------------------------------------------ 20- 4.1 Architecture I ------------------------------------------------------------------------------- 20- 4.1.1 Modules 1 & 2 ----------------------------------------------------------------------- 20- 4.1.2 Modules 3 & 4 ----------------------------------------------------------------------- 22- 4.1.3 Fixed-point Analysis ---------------------------------------------------------------- 25- 4.1.4 Chip Implementation and Comparison ------------------------------------------- 27- 4.2 Architecture II ------------------------------------------------------------------------------ 29- 4.2.1 The Proposed MMAS Scheme ---------------------------------------------------- 31- 4.2.2 Chip Implementation and Comparison ------------------------------------------- 34- Chapter 5 The MDF-based Multimode FFT Processor ---------------------------------------- 36- 5.1 The Proposed FRCMDF Architecture --------------------------------------------------- 36- 5.1.1 Module 1 ----------------------------------------------------------------------------- 37- 5.1.2 Module 2 ----------------------------------------------------------------------------- 39- 5.1.3 Application-Oriented Voltage Scaling (AVS) ----------------------------------- 41- 5.2 Dual-Optimized Multiplication Scheme ------------------------------------------------ 43- 5.2.1 PUEC CORDIC Unit --------------------------------------------------------------- 43- 5.2.2 Mixed-Simplification CMU ------------------------------------------------------- 47- 5.2.3 Evaluation -------------------------------------------------------------------------- 49- 5.3 Chip Implementation ---------------------------------------------------------------------- 51- 5.3.1 Measurement Strategy -------------------------------------------------------------- 51- 5.3.2 Measurement Results and Comparison ------------------------------------------ 52- 5.4 SQNR Performance ---------------------------------------------------------------------- 56- Chapter 6 The Memory-based Multimode FFT Processor----------------------------------- 59- (A Draft Design for Future Work) 6.1 The Proposed Architecture ------------------------------------------------------------- 59- 6.2 Data Access and Memory Allocation Schemes (Draft)------------------------------- 60- 6.2.1 (Data Access) Schemes for WMAM FFTs -------------------------------------- 60- 6.2.2 (Data Access) Schemes for WLAN/UWB FFTs -------------------------------- 63- 6.3 The Proposed Multimode FFT Kernel (Draft)---------------------------------------- 64- 6.3.1 Kernel Operations for WMAN FFTs --------------------------------------------- 65- 6.3.2 Kernel Operations for WLAN/UWB FFTs -------------------------------------- 68- 6.4 Chip Implementation and Comparison (Draft) --------------------------------------------- 69- Chapter 7 Conclusion ------------------------------------------------------------------------------ 71- Bibliography ------------------------------------------------------------------------------------------- 73-

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