研究生: |
湯松年 Tang, Song-Nien |
---|---|
論文名稱: |
適用於無線個人/區域/都會網路應用之多模式快速傅立葉處理器設計 Design of the Multimode FFT Processors for WPAN/WLAN/WMAN Applications |
指導教授: |
張慶元
Chang, Tsin-Yuan |
口試委員: |
袁正泰
黃家齊 謝明得 馬席彬 黃元豪 |
學位類別: |
博士 Doctor |
系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
論文出版年: | 2011 |
畢業學年度: | 100 |
語文別: | 英文 |
論文頁數: | 76 |
中文關鍵詞: | 傅立葉轉換 |
相關次數: | 點閱:4 下載:0 |
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隨著無線數據通訊的需求,無線區域網路(Wireless Local Area Network; 簡稱
WLAN),無線都會網路(Wireless Metropolitan Area Network; 簡稱WMAN)以及無線個
人網路(Wireless Personal Area Network; 簡稱WPAN)已被廣泛地開發並應用在系統平台
上。針對此三種無線網路,相關的標準也在近期被提出,其中主要包括了IEEE 802.11n(因
應WLAN),IEEE 802.11e/m(因應WMAN)以及IEEE 802.15.3a/c(因應WPAN)。在上述
三種網路系統的實體層設計裡, 正交分頻多工(Orthogonal Frequency Division
Multiplexing; 簡稱OFDM)是其主要的核心技術,而傅立葉轉換(Fast Fourier Transform;
簡稱FFT)器則是OFDM 系統所需用的關鍵性零組件。
從系統整合的觀點來看,為了可彈性地根據速度需求與所處環境來進行無線數據的
擷取,一個擁有多模式(Multimode)傅立葉轉換器的三重無線個人/區域/都會網路系統是
具有開發上的實用性。因此在本篇論文中,我們以傅立葉轉換硬體的兩種主要方案,即
管線式(pipelined)和基於記憶體式(memory-based)的架構為基礎,提出適用於三重無線個
人/區域/都會網路應用的多模式傅立葉轉換器設計。在管線式傅立葉轉換器的架構上,我們首先針對無線個人網路應用,以多路徑延遲
迴授(multipath delay feedback; 簡稱MDF)結構作基礎,提出一個具有高輸出入率
(throughput rate)之2048 點的傅立葉轉換器。藉由所提出之新穎的乘法化簡以及多路徑
數值縮放(multidata scaling)方法,我們可在所呈現的架構中改善硬體效能。此外,為了
進一步達到記憶體相關的節能,我們也在本篇論文中提到混合式記憶體擷取調度
(mixed-memory-access-scheduling; MMAS)的方案。針對多模式運作的需求,我們也進階
提出了一個靈活基數組態(flexible-radix-configuration; FRC)的MDF 架構。該架構能針對
無線個人/區域/都會網路的應用,以有效益的硬體方式來執行相關的高輸出入率和可變
點數並多重串數的傅立葉轉換運算。基於所提出的FRCMDF 結構,一個雙重最佳化
(dual-optimized)的乘法方案也被陳明以進一步改善面積與功率的效益。此外,我們所提
出的組態方式可針對跨模式下的功率可延展性(power scalability)提供了架構性的支援。
除了根源於MDF 架構的作法,基於記憶體式(memory-based)的傅立葉轉換器架構
也同樣被考量來針對無線區域網路,無線都會網路以及超寬頻(Ultra Wideband; UWB;
即WPAN 系統的早期規格)的應用作多模式傅立葉轉換器的開發。在本篇論文中,我們
亦提出一個基於記憶體式之多模式快速傅立葉處理器。該處理器可藉由新穎的記憶體配
置方法連同一個節能的多模式傅立葉轉換核心,來有效率地執行無線區域/都會/超寬頻
網路相關的傅立葉轉換運算。
[1] A. Batra et al., “Multi-Band OFDM Physical Layer Proposal for IEEE 802.15 Task
Group 3a,” IEEE P802.15-03/268r3, Mar. 2004.
[2] IEEE 802.15.3c-2009: Part 15.3: Wireless Medium Access Control (MAC) and Physical
Layer (PHY) Specifications for High Rate Wireless Personal Area Networks (WPANs).
[3] Y. Chen, Y.-C. Taso and C.-Y. Lee, “An indexed-scaling pipelined FFT processor for
OFDM-based WPAN applications,” IEEE Trans. Circuits Syst. II: Express Briefs, vol.
55, no. 2, pp. 146–150, Feb. 2008.
[4] Y.-W. Lin, H.-Y. Liu and C.-Y. Lee, ”A 1-GS/s FFT/IFFT processor for UWB
applications,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1726-1735, Aug. 2005.
[5] S.-N Tang, J.-W. Tsai and T.-Y. Chang, “A 2.4 GS/s FFT processor for OFDM based
WPAN applications,” IEEE Trans. Circuits Syst. II: Express Briefs, vol. 57, no. 6, pp.
451–455, June 2010.
[6] IEEE 802.11n-2009: Part 15.3: Wireless LAN Medium Access Control (MAC) and
Physical Layer (PHY) Specifications.
[7] IEEE 802.16e-2005: Part 16: Air Interface for Fixed and Mobile Broad-band Wireless
Access Systems.
[8] Y.-W. Lin and C.-Y. Lee, “Design of an FFT-IFFT Processor for MIMO OFDM
Systems,” IEEE Trans. Circuits Syst. I: Regular Papers, vol. 54, no. 4, pp. 807–815,
Apr. 2007.
[9] Y. Chen, Y.-W. Lin, and C.-Y. Lee, “A Block Scaling FFT/IFFT Processor for WiMAX
Applications,” in Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC), pp. 203-206,
Nov. 2006.
[10] C.-M. Chen, C.-C. Hung and Y.-H. Huang, “An energy-efficient partial FFT processor
for the OFDMA communication system,” IEEE Trans. Circuits Syst. II: Express Briefs,
vol. 57, no. 2, pp. 136–140, Feb. 2010.
[11] Y.-T. Lin, P.-Y. Tsai, and T.-D. Chiueh, "Low-power variable length fast Fourier
transform processor," in Proc. IEE Comput. -Digit. Tech., vol. 152, no. 4, pp. 499-506,
July 2005.
[12] G. Zhong, F. Xu, and A. N.Willson, “A power-scalable reconfigurable FFT/IFFT IC
based on a multi-processor ring,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp.
483–495, Feb. 2006.
[13] R. Chidambaram, R. van Leuken, M. Quax, I. Held and J. Huisken, “A multistandard
FFT processor for wireless system-on-chip implementation,” in Proc. IEEE Int. Symp.
Circuits Syst. (ISCAS), 2006, pp. 1099–1102.
[14] Y.-T. Hwang, Y.-J. Chen and W.-D. Chen, “Scalable FFT kernel designs for MIMO
OFDM based communication Systems”, in Proc. IEEE Conf. TENCON, Oct. 2007,
pp.1-4.
[15] Y. Chen, Y.-W. Lin, Y.-C. Taso and C.-Y. Lee, ”A 2.4-Gsample/s DVFS FFT
processor for MIMO OFDM communication systems,” IEEE J. Solid-State Circuits, vol.
43, no. 5, pp.1260- 1273, May 2008.
[16] B. M. Baas, "A low-power, high-performance, 1024-point FFT processor," IEEE J.
Solid-State Circuits, vol. 34, no. 3, pp. 380-387, Mar. 1999.
[17] H. Shousheng and M. Torkelson, “Designing pipeline FFT processor for OFDM
(de)modulation,” in Proc. URSI Int. Symp. Signals, Syst. Electron., 1998, pp. 257–262.
[18] J. O‟Brien, J. Mather, and B. Holland, “A 200 MIPS single-chip 1 k FFT processor,” in
IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, vol. 36, 1989, pp. 166–167.
[19] Y.-W. Lin, H.-Y. Liu, and C.-Y. Lee, “A dynamic scaling FFT processor for DVB-T
applications,” IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 2005–2013, Nov. 2004.
[20] B. G. Jo and M. H. Sunwoo, “New continuous-flow mixed radix (CFMR) FFT using
novel in-place strategy,” IEEE Trans. on Circuits and Systems, Part-I: Regular Papers,
vol. 52, pp. 911–919, May. 2005.
[21] G. Zhang and F. Chen, “Parallel FFT with CORDIC for ultra wide band,” in Proc. 15th
IEEE Int. Symp. Personal, Indoor and Mobile Radio Commun. (PIMRC), Sep. 2004, vol.
2, pp. 1173-1177.
[22] S.-j. Huang and S.-G. Chen, “A Green FFT Processor with 2.5-GS/s for IEEE 802.15.3c
(WPANs),” in Proc. Int. Conf. Green Circuits Syst. (ICGCS), June 2010, pp. 9-13.
[23] S.-N Tang, J.-W. Tsai and T.-Y. Chang, “An Energy-efficient MMAS FFT processor for
high-rate WPAN applications,” IEEE Int. Symp. Consumer Electron. (ISCE), June 2010,
pp. 446–449.
[24] E. Bidet, D. Castelain, and P. Senn, “A fast single-chip implementation of 8192 complex
point FFT,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 300–305, Mar. 1995.
[25] T. Lenart and V. Öwall, “A 2048 complex point FFT processor using a novel data
scaling approach,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2003, pp. 45–48.
[26] T. Lenart and V. Öwall, “Architectures for dynamic data scaling in 2/4/8K pipeline FFT
cores,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 11, pp.
1286–1290, Nov. 2006.
[27] C. L. Hung, S. S. Long, and M. T. Shiue, "A low power and varaible-length FFT
processor design for flexible MIMO OFDM systems," in Proc. IEEE Int. Symp. Circuits
Syst. (ISCAS), 2009, pp. 705-708.
[28] M. Shin, and H. Lee, “A high-speed, four-parallel radix-24 FFT processor for UWB
applications,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2008, pp. 960–963.
[29] J. –Y. Oh and M. S. Lim, “Area and power efficient pipeline FFT algorithm,” in Proc.
IEEE Workshop on Signal Processing Systems (SiPS), 2005, pp. 520-525.
[30] K. Maharatna, E. Grass, and U. Jagdhold, “A 64-point fourier transform chip for
high-speed wireless lan application using OFDM,” IEEE J. Solid-State Circuits, vol. 39,
no. 3, pp. 484–493, Mar. 2004.
[31] J. Mathew, K. Maharatna, D. K. Pradhan, and A. P. Vinod, "Exploration of power
optimal implementation technique of 128-pt FFT/IFFT for WPAN using pseudo-parallel
datapath structure," in Proc. IEEE Int. Conf. Communication Systems (ICCS) , 2006,
pp. 1-5.
[32] A. M. Despain, “Fourier transform computers using CORDIC iterations,” IEEE Trans.
Comput., vol. 23, no. 10, pp. 993–1001, Oct. 1974.
[33] M. Elgebaly and M. Sachdev, “Variation-aware adaptive voltage scaling system,” IEEE
Trans. VLSI Syst., vol. 15, no. 5, pp. 560–571, May 2007.
[34] Neil. H. E. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems
Perspective. Boston, NJ: Addison-Wesley, 2004.
- 76 -
[35] S.-M. Kim, J.-G. Chung and K. K. Parhi, “Low error fixed-width CSD multiplier with
efficient sign extension,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process.,
vol. 50, no. 12, pp. 984–993, Dec. 2003.
[36] Y.-H. Chen, T.-Y. Chang, and C.-Y. Li, “High throughput DA-based DCT with high
accuracy error-compensated adder tree,” IEEE Trans. VLSI Syst., vol. 19, no.4,
pp.709-714, April 2011.
[37] K.-J. Cho, K.-C. Lee, J.-G. Chung and K. K. Parhi, “Design of low-error fixed-width
modified booth multiplier,” IEEE Trans. VLSI Syst., vol. 12, no. 5, pp. 522–531, May
2004.
[38] E. Antelo, J. Villalba, D. Bruguera, and E. Zapata, “High performance rotation
architectures based on the radix-4 CORDIC algorithm,” IEEE Trans. Comput., vol. 46,
no. 8, pp. 855–870, Aug. 1997.
[39] R. Sarmiento, F. Tobajas, V. de Armas, R. Esper-Chain, J.F. Lopez, J.A. Montiel-
Nelson, and A. Nunez, „A CORDIC processor for FFT computation and its
implementation using gallium arsenide technology‟, IEEE Trans. VLSI Syst., vol. 6, no.
1, pp. 18–30, Mar. 1998.
[40] C.-S. Wu, A.-Y. Wu, and C.-H. Lin, “A high-performance/low-latency vector rotational
CORDIC architecture based on extended elementary angle set and trellis-based
searching schemes,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50,
no. 9, pp. 589–601, Sep. 2003.
[41] C.-H. Lin and A.-Y. Wu, “Mixed-scaling-rotation CORDIC (MSR- CORDIC) algorithm
and architecture for high-performance vector rotational DSP applications,” IEEE Trans.
Circuits Syst. I: Regular Papers, vol. 52, no. 11, pp. 2385–2396, Nov. 2005.
[42] H.-C. Hsu, K.-B. Lee, Nelson Y.-C. Hang, and T.-S Chang, “Architecture design of
shape-adaptive discrete cosine transform and its inverse for MPEG-4 video coding,”
IEEE Trans. Circuits Syst. Video Technol., vol. 18, no. 3, pp. 375–386, Mar. 2008.