為了符合Ultra large-scale integration (ULSI)製程技術中元件微縮的趨勢，改採用高介電係數材料取代二氧化矽做為介電層。但是高介電係數氧化層的製程技術易導致界面氧化層的增生，這造成等效氧化層厚度微縮上的困難。之外，因為高介電係數介電層和矽基板間的界面品質不良導致載子遷移率下降。為了克服這些挑戰，高介電係數介電層，矽鍺或鍺通道等研究已經引起金氧半電晶體研究領域的關注。
然而傳統的二氧化鉿(斜方晶系)因為介電係數介於15~20之間，難以將等效氧化層厚度微縮到0.9 nm以下，因此更高介電係數的介電層是值得研究。因為氧化鈦的介電係數約達60，我們使用微量的鈦金屬摻雜入二氧化鉿。鈦與二氧化鉿的堆疊結構在經過金屬閘極後600 oC的退火製程，等效氧化層厚度可低於0.76 nm。但在超過700 oC退火處理後的元件電特性會明顯衰退。
為了進一步微縮元件的等效氧化層厚度，保持低閘極漏電流與維持元件可靠度是非常重要的，而四方晶系的二氧化鉿(k>30)被列為候選者之一。將氯電漿應用在堆疊高介電係數介電層的前置處理，使高介電係數(k>30)的四方晶體結構可以在650oC的退火製程下產生。藉由穿透式電子顯微鏡以及電容電壓曲線的量測結果，四方晶向二氧化鉿的介電係數約達35。光學能隙的量測值顯示，二氧化鉿在四方晶向和斜方晶向的能隙是相似的。
電子和電洞遷移率在鍺基板上比起矽基板分別高出2倍和4倍，因此鍺通道成為解決高介電係數介電層所造成載子遷移率下降問題的候選者。首先我們以2 nm的矽蓋堆疊在鍺濃度7~32%的矽鍺基板上。基於金氧半元件在閘極漏電和可靠度的特性，用以提升載子遷移率的最佳化鍺濃度是在20%。後續我們再透過電漿浸潤式離子佈植(PIII)氮化處理矽鍺通道的金氧半元件，實驗結果顯示電特性會有顯著的提升。例如stress-induced leakage 可以減少50%， stress-induced flatband voltage shifts 也減少超過33%。此外在30%鍺含量的矽鍺虛擬基板，可藉由電漿浸潤式離子佈植對元件進行氮化工程，使等效氧化層的厚度微縮到0.96 nm。
對於搭配超薄高介電係數氧化層的金氧半元件，為了同時達成在介電層與基板中高品質的界面層以及提高載子遷移率，我們提出了矽鍺超晶格結構的P型金氧半電晶體。實驗的結果顯示，電特性可以有顯著的提升。P型金氧半電晶體的電洞遷移率高出矽基板1倍，在汲極電流開關比率可達10的8次方而且等效氧化層厚約1 nm。源極與汲極的載子可在650oC時活化，和高介電值介電層的製程相容。
最後，一個具有超低等效氧化層厚度(0.5 nm)和可接受的漏電流的鍺金氧半元件被提出。如此卓越的電特性歸功於具有高介電係數和大能隙的二氧化鉿。以四方晶向的二氧化鉿為介電層的鍺金氧半元件有較低的漏電和較好的熱穩定性。透過in-situ的H2O電漿製程，可得一介電常數約13的界面氧化層。此外，透過H2O電漿形成的界面層有較高的Ge4+含量，所以有較小的介面缺陷密度和遲滯現象。

In order to meet the requirement of device scaling for ultra large scale integration (ULSI) technology, a high dielectric constant (high-k) gate insulator should be applied in MOS devices to further scale down the equivalent oxide thickness (EOT). However, regrowth of the interfacial layer may be induced by high-k dielectric processes, which render EOT scaling difficult. In addition, carrier mobility is degraded because of the poor quality of the high-k/Si interface. To overcome these challenges, studies of high-k gate dielectrics, SiGe and Ge channel have attracted much attention in the research fields of MOS field-effect-transistor (MOSFET) devices.
The dielectric constant k of the traditional HfO2 dielectric (monoclinic phase), which is approximately 15 to 20, is not sufficiently high to reduce the EOT to below 0.9 nm for MOS devices. Thus, some exotic higher-k dielectrics deserve investigation. Because of k ≈ 60 for TiO2, HfO2 doped with Ti is studied. An EOT of 0.76 nm is obtained for a sample with a Ti/HfO2 higher-k dielectric after post-metallization annealing (PMA) at 600 °C. As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.
For reducing the EOT value, it is crucial to maintain low gate leakage current and the reliability of the MOS device. The tetragonal phase HfO2 (k > 30) is proposed to be a higher-k dielectric candidate. t-HfO2 can be formed by using a Cl2 plasma treatment at the HfO2/Si interface after post-deposition annealing at 650 °C. Using the results of cross-sectional transmission electron microscopy and capacitance–voltage measurement, we estimated the value of this t-HfO2 to be approximately 35. The optical bandgap value for t-HfO2 is similar to that of the monoclinic.
Because Ge can offer twice the electron mobility and four times better hole mobility than Si, Ge is a promising candidate to resolve the issue of mobility degradation by high-k dielectrics. At first, a thin Si layer was grown upon SiGe channel layer as a capping layer. Different Ge contents from 7% to 32% in SiGe channel on electrical characteristics of MOS device were investigated. Based on gate leakage and reliability properties of MOS devices, the optimal Ge content in SiGe channel to achieve sufficient mobility enhancement is around 20%.
Further, high-k gated MOS devices with a SiGe channel and nitridation treatment using plasma immersion ion implantation (PIII) were studied. Experimental results indicate that the electrical characteristics of high-k dielectric can be obviously improved by PIII nitridation. For instance, the values of stress-induced leakage are reduced by more than 50%, and the values of stress-induced-flat-band voltage shifts are reduced by more than 33%. Moreover, the EOT value of the MOS device with 30% Ge content in the SiGe channel and PIII nitridation can be reduced to 9.6 A.
In order to achieve a high-quality interfacial layer between the high-k dielectric and the Si substrate as well as to enhance the carrier mobility degraded by an ultrathin high-k gate dielectric, a pMOSFET device with a novel super-lattice (SL) Si/Ge channels is proposed. Experimental results show that the electrical characteristics of the MOSFET can be obviously improved by using the SL virtual substrate. The peak hole mobility of the pMOSFET device with SL is enhanced by approximately 100% than that with Si. Moreover, the on-off ratio of the Id–Vg curve is more than eight orders, and the EOT value of the gate dielectric is ~1 nm. The source/drain activation temperature of 650 °C is particularly suitable to the high-k dielectric process.
Finally, a Ge MOS device with an ultralow EOT of ~ 0.5 nm and acceptable leakage current of 0.5A/cm2 is presented in this work. The superior characteristics can be attributed to a tetragonal HfO2 with a higher k value (k~31) and comparable band gap. Besides, a Ge MOS device with t-HfO2 also shows a lower leakage current and better thermal stability. The IL with k~13 can be formed by in-situ H2O plasma treatment. Moreover, a Ge MOS device with the IL grown by H2O plasma shows smaller interface trap density and hysteresis effects due to a high composition of Ge+4.

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