能量的耗損讓晶片的發展要符合摩爾定律成為一個極大的挑戰，由於單電子電晶體 (Single-Electron Transistor) 在室溫下的操作過程中屬於低功耗，其裝置可望成為一個可靠的低功耗裝置取代原本的互補式金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor)藉此來符合摩爾定律。目前為止，已有針對單電子電晶體架構的自動化合成方法被提出。最新的合成方法著重在單電子電晶體個數上的縮減。然而，對於單電子電晶體架構來說，面積是其寬高的乘積，而非個數總和。由於單電子電晶體架構的高度通常固定為電路主要輸入(Primary Input)的個數，因此，本論文提出一套新的自動化合成方法專注於縮小單電子電晶體架構的寬度來最小化合成後的單電子電晶體架構的面積。我們實驗包含四個技術—乘積項的縮減、基於分支後分享(Branch-Then-Share)的變數排序、單電子電晶體配置架構的放鬆以及基於分支後分享(Branch-Then-Share)的乘機項排序。從實驗結果中顯示，相比於目前最新的單電子電晶體自動化合成方法，我們所提出的方法可以節省下45%的寬度。

Power consumption has become one of the primary challenges to meet the Moore’s law. For reducing power consumption, Single-Electron Transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore’s law due to its ultra-low power consumption in operation. Prior works have proposed automated mapping approaches for SET arrays which focus on minimizing the number of hexagons in SET arrays. However, the area of an SET array is the product of the bounded height and bounded width, and the height is usually equal to the number of inputs in the Boolean function. Consequently, in this work, we focus on the width minimization in the mapping of the SET arrays. Our approach consists of techniques of product term minimization, variable reordering, product term reordering and architecture relaxation. The experimental results show that the proposed approach saves 45\% of width compared with the state-of-the-art for a set of MCNC and IWLS 2005 benchmarks.

[1] [Online]. Available: http://iwls.org/iwls2005/benchmarks.html
[2] N. Asahi, M. Akazawa, and Y. Amemiya, Single-electron logic device based on the binary dicision diagram," IEEE Trans. Electron Devices, vol. 44, pp. 1109{1116, 1997.
[3] R. E. Bryant, Graph-based algorithms for boolean function manipulation," IEEE Trans. Computers, vol. 35, pp. 677{691, 1986.
[4] Y.-C. Chen, S. Eachempati, C.-Y. Wang, S. Datta, Y. Xie, and V. Narayanan, Automated mapping for recongurable single-electron transistor arrays," in Proc. Design, Automation Conference, 2011, pp. 878-883.
[5] Y.-C. Chen, S. Eachempati, C.-Y. Wang, S. Datta, Y. Xie, and V. Narayanan, A synthesis algorithm for recongurable single-electron transistor arrays," ACM Journal on Emerging Technologies in Computing Systems, vol. 9, 2013.
[6] Y.-C. Chen, C.-Y. Wang, and C.-Y. Huang, Verication of recongurable binary decision diagram-based single-electron transistor arrays," IEEE Trans. on Computer-Aided Design, vol. 32, pp. 1473-1483, 2013.
[7] C.-E. Chiang, L.-F. Tang, C.-Y.Wang, C.-Y. Huang, Y.-C. Chen, S. Datta, and V. Narayanan, On recongurable single-electron transistor arrays synthesis using reordering techniques," in Proc. Design, Automation and Test in Europe, 2013, pp. 1807-1812.
[8] S. Eachempati, V. Saripalli, N.Vijaykrishnan, and S. Datta, Recongurable bdd-based quantum circuits," in Proc. Int. Symp. on Nanoscale Architectures, 2008, pp. 61-67.
[9] H. Hasegawa and S. Kasai, Hexagonal binary decision diagram quantum logic circuits using schottky in-plane and wrap gate control of gaas and ingaas nanowires," Physica E: Low-dimensional Systems and Nanostructures, vol. 11, pp. 149-154, 2001.
[10] P. K. Karre, Room temperature operational single electron transistor fabricated by focused ion beam deposition," Journal of Applied Physics, vol. 102, pp. 034 316-024 316-4, 2007.
[11] S. Kasai, Y. Amemiya, and H. Hasegawa, Gaas schottky wrap-gate binary-decision-diagram devices for realization of novel single electron logic architecture," in Proc. International Electron Devices Meeting, 2000, pp. 585-588.
[12] S. Kasai, M. Yumoto, and H. Hasegawa, Fabrication of gaas-based integrated 2-bit half and full adders by novel hexagonal bdd quantum circuit approach," in Proc. Int. Symp. on Semiconductor Device Research, 2001, pp. 622-625.
[13] P.-Y. Kuo, C.-Y. Wang, and C.-Y. Huang, On rewiring and simplication for canonicity in threshold logic circuits," in Proc. International Conf. on Computer-Aided Design, 2011, pp. 396-403.
[14] C.-C. Lin, C.-Y. Wang, Y.-C. Chen, and C.-Y. Huang, Rewiring for threshold logic circuit minimization," in Proc. Design, Automation and Test in Europe, 2014.
[15] L. Liu, V. Saripalli, V. Narayanan, and S. Datta, Device circuit co-design using classical and non-classical iii-v multi-gate quantum-well fets (muqfets)," in Proc. International Electron Devices Meeting, 2011, pp. 83-86.
[16] S. Muroga, Threshold Logic and its Applications. John Wiley, 1971.
[17] H. W. C. Postma, T. Teepen, Z. Yao, M. Grifoni, and C. Dekker, Carbon nanotube single-electron transistors at room temperature," Science, vol. 293, pp. 76-79, 2001.
[18] Y. T. Tan, T. Kamiya, Z. A. K. Durrani, and H. Ahmed, Room temperature nanocrystalline silicon single-electron transistors," Journal of Applied Physics, vol. 94, pp. 633{637, 2003.
[19] S. Yang, \Logic synthesis and optimization benchmarks user guide version 3.0," in Tech. Report, Microelectronics Center of North Carolina, 1991, pp. 502-508.
[20] R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, \Synthesis and optimization of threshold logic networks with application to nanotechnologies," in Proc. Design, Automation and Test in Europe, 2004, pp. 904-909.
[21] R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, Synthesis and optimization of threshold logic networks with application to nanotechnologies," in Proc. Design, Automation and Test in Europe, 2004, pp. 904-909.
[22] L. Zhuang, L. Guo, and S. Y. Chou, \Silicon single-electron quantum-dot transistor switch operating at room temperature," in Applied Physics Letters, 1998, pp. 1205-1207.