研究生: |
郭岳嘉 Yueh-Chia Kuo |
---|---|
論文名稱: |
類循環低密度位元檢查碼之多層次編碼應用 Application of Quasi-Cyclic Low-Density Parity-Check Codes to Multilevel Coding |
指導教授: |
趙啟超
Chi-Chao Chao |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 通訊工程研究所 Communications Engineering |
論文出版年: | 2005 |
畢業學年度: | 93 |
語文別: | 英文 |
論文頁數: | 45 |
中文關鍵詞: | 低密度位元檢查碼 、類循環低密度位元檢查碼 、多層次編碼 、平行獨立解碼 、迴圈矩陣 、歐氏幾何碼 |
外文關鍵詞: | LDPC, quasi-cyclic LDPC, multilevel coding, parallel independent decoding, circulant matrix, euclidean geometry codes |
相關次數: | 點閱:4 下載:0 |
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傳統通訊主要是傳輸二進位數位碼(Binary Codes),隨著傳輸速度不斷提升,在不增加額外頻寬的情形下,衍生出將編碼和調變有效地結合在一起的傳輸方式取代傳統的二進位數位碼。其中最著名的方式為:多層次編碼(Multilevel Coding)和網格編碼調製(Trellis-Coded Modulation)。多階段解碼(Multistage Decoding)和平行獨立解碼(Parallel Independent Decoding)為多層次編碼的主要的解碼方式。在本篇論文我們將採用較具彈性的多層次編碼和次佳化但有效率的平行獨立解碼為整個系統的基本架構。對於多層次編碼而言,每層都可以輸入任意的二進位數位碼,我們將使用類循環低密度位元檢查碼(Quasi-Cyclic Low-Density Parity-Check Codes)作為每層的編碼。根據歐氏幾何碼(Euclidean Geometry Codes)的特性,我們可建立迴圈矩陣(Circulant Matrix)。類循環低密度位元檢查碼期編碼是藉由分解迴圈矩陣而獲得其同位檢查矩陣(Parity Check Matrix),並且其編碼程序可以使用簡單線性移位暫存器得到對應的字碼。各層次對應的同位檢查矩陣,由於是由迴圈矩陣所分解形成的,因此同位檢查矩陣之間有代數關係存在,也就是說較低層次的同位檢查矩陣,是由高層次的同位檢查矩陣分解形成的,利用這種分解關係,我們將可以大大地簡化多層次編碼的編碼和解碼程序的硬體複雜度,且不失去整個系統的效能,於論文中我們提出一個編碼和解碼程序的基本架構。根據參考文獻,平行獨立解碼的解碼方式,將受限於所對應的調變方式,在論文中我們將比較不同的調變方式,其對整個系統的影響程度。
Multilevel coding (MLC) is a well-known coded modulation scheme proposed to achieve
both power and bandwidth eciency. Multistage decoding (MSD) and parallel independent
(PID) decoding are two decoding methods proposed for the MLC scheme. Since PID is
a suboptimal but more eective decoding strategy than MSD, we consider the MLC/PID
scheme here. Any codes, e.g., block codes, convolutional codes, or concatenated codes, can
be used as the component codes in the MLC scheme. In this thesis, we use the quasi-cyclic
low-density parity-check (QC-LDPC) codes as the component codes. The construction of
these codes is based on decomposition of circulants constructed from the Euclidean geometry.
The encoding and decoding of the MLC scheme can be simplied based on the structural
relations between the parity-check matrices of component codes. Therefore, we can greatly
reduce the hardware complexity of the proposed MLC/PID scheme. Finally, we compare the
simulated performance of the proposed MLC schemes employing QC-LDPC codes with those
using other block codes and show the eect of the signal mapping rule on performance.
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