研究生: |
李侑紘 You-Hung Lee |
---|---|
論文名稱: |
高速除頻器之設計與基底雜訊對其電路特性影響之研究 High Speed Frequency Divider Design and the Substrate Noise Coupling on Circuit Characteristics |
指導教授: |
徐碩鴻
Shuo-Hung Hsu |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2007 |
畢業學年度: | 95 |
語文別: | 英文 |
論文頁數: | 55 |
中文關鍵詞: | 除頻器 、基底雜訊 |
外文關鍵詞: | Frequency Divider, Substrate Noise |
相關次數: | 點閱:4 下載:0 |
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本報告最重要的核心重點,在於如何設計不同的高頻除頻器,並且使用標準的CMOS 0.18□m製程。
接著提出新的類比式除頻器架構稱之為Source-degeneration Injection-Locked Frequency Divider (SILFD)。是基於MOS開關的概念耦合到一般所知的LC振盪器cross coupled pair的源級。利用可變電容以及source degeneration有效率地增加操作頻率和除頻範圍。輸入訊號透過開關的電晶體比起傳統架構除頻器的可以設計地比較小。操作頻率最高可達24.8GHz,且當輸入強度為5dBm時除頻範圍達5GHz,總功率消耗約為17mW。此外,利用回授電阻的數位式除頻器在此提出。此除頻器操作在18GHz是使用回授電阻增加操作頻率並擁有較小的面積。當輸入強度為0dBm時,除頻範圍達2.5GHz,總功率消耗約為45mW。
本論文也研究基底雜訊對其電路特性的影響,包含了雜訊經由數種不同的pad輸入對ILFD輸出的影響之比較。另外,電感的guard ring接地或浮空對ILFD的影響也在本論文中比較與討論。當雜訊強度增加時,IM2和IM3會成線性增加並且當雜訊強度為20~25dBm時接近飽和。而當除頻器的輸入訊號愈來愈大,IM spur將會愈受到抑制。本文中證明了接地的(grounded)電感guard ring提供了一個比浮空的(floated)電感guard 較好的基底雜訊免疫度約5dBm。
The main focus of this work is to design high speed frequency dividers based on currently CMOS 0.18□m technology.
A new topology analog divider called Source-degeneration Injection-Locked Frequency divider (SILFD) is proposed. The divider is based on a MOS switch coupled to the sources of the cross coupled pair of well-known LC oscillator. With the varactors and source degeneration, the oscillation frequency and locking rang increase efficiently. The incident signal is provided through the switch transistor, which can be designed much smaller than conventional. The maximum operating frequency is 24.8GHz and the locking range is about 5GHz as input power is 5dBm. The total power consumption is almost 17mW. Besides, a digital frequency divider with feedback resistor is designed. The designed frequency divider uses feedback resistor to increase the operation frequency and has the smaller chip area under the operation frequency which is 18GHz. The locking range is about 2.5GHz as input power is 0dBm. The total power consumption is almost 45mW.
This thesis also investigates the effect of substrate noise on circuit characteristics, including the comparison of an ILFD output performances with the noise injected via several different pads. The IM2 and IM3 linearly increase with noise power injection and saturate at noise power near 20~25dBm. As input power of the divider increases, the IM spur would be suppressed. Furthermore, the effect of the inductor grounded or floated on an ILFD is compared and discussed in this thesis also. It is demonstrated the grounded inductor guard ring provides a better immunity from substrate noise than the floated one by 5dBm.
[1] H. R. Rategh, H. Samavati, and Thomas H. Lee, “A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver,” IEEE J. Solid-State Circuits, vol. 35, issue 5, pp. 780 – 787, May 2000.
[2] H. R. Rategh and T. H. Lee, “Superharmonic injection-locked frequency dividers,” IEEE J. Solid-State Circuits, vol. 34, pp. 813–821, June 1999.
[3] H. R. Rategh and T. H. Lee, “Superharmonic injection locked oscillators as low power frequency dividers,” in Symp. VLSI Circuits Dig., pp. 132–135, 1998.
[4] A. Mirzaei, “Transient analysis of injection-locked frequency dividers,” IEEE Circuits and Systems, vol. 3, pp. III-381 - III-384, Aug. 2002.
[5] A. Nordbotten, “LMSD Systems and their Application,”IEEE Communications Magazine, vol. 38, Issue 6, pp. 150 – 154, June 2000.
[6] S. Y. Seidel, “Radio Propagation and Planning at 28GHz for Local Multipoint Distribution Service (LMDS),” IEEE Antennas and Propagation Society International Symposium, vol. 2, pp. 622 – 625, June 1998.
[7] H. Sari, “Some Design Issues in Local Multipoint Distribution Systems,” IEEE Signals, Systems, and Electronics, pp. 13 – 19, Sept.- Oct. 1998.
[8] J. H. C. Zhan, K. Maurice, J. S. Duster, K. T. Kornegay, “ANALYSIS OF EMITTER DEGENERATED LC OSCILLATORS USING BIPOLAR TECHNOLOGIES,” Circuits and Systems, vol. 1, pp. I-669 - I-672, May 2003.
[9] J. H. C. Zhan, K. Maurice, J. S. Duster, K. T. Kornegay, “Analysis and Design of Negative Impedance LC Oscillators Using Bipolar Transistors,” Circuits and Systems I: Fundamental Theory and Applications, vol. 50, pp. 1461 – 1464, Nov. 2003.
[ 0] J. H. C. Zhan, J. S. Duster, K. T. Kornegay, “A 24.9-GHz Emitter-Degenerated SiGe Bipolar VCO,” Bipolar/BiCMOS Circuits and Technology Meeting, pp. 71 – 74, Sept. 2003.
[ 1] T. H. Lee and J. F. Bulzacchelli, “A 155-MHz clock recovery delay-and phase-locked loop,” IEEE J. Solid-State Circuits, vol. 27, pp. 1736-1746, Dec. 1992.
[ 2] W.Z. Chen and J. T. Wu, “A 2-V 2-GHz BJT Variable Frequency Oscillator,” IEEE J. Solid-State Circuits, vol. 33, pp. 1406-1410, Sep. 1998.
[13] J. Lee, B. Razavi, “A 40-GHz Frequency Divider in 0.18-um CMOS Technology,” IEEE J. Solid-State Circuits, vol. 39, Issue 4, pp. 594 – 601, April 2004.
[14] K. Yamamoto, M. Fujishima, “55GHz CMOS Frequency Divider with 3.2GHz Locking Range,” IEEE Solid-State Circuits Conference, pp. 135 – 138, Sept. 2004.
[15] M. Alioto, G. Di Cataldo, and G. Palumbo, “Design of low-power high-speed bipolar frequency dividers,” Electronics Letters, vol. 38, pp. 158-160, Feb. 2002.
[16] S. Mohan, et al, “Bandwidth extension in CMOS with optimized on-chip inductors”, IEEE J. Solid-State Circuits, vol. 35, no.3, pp. 346-355, March 2000.
[ 7] N. Ohkawa, “Fiber-optic multigigabit GaAs MIC front-end circuit with inductor peaking,” J. Lightwave Tech., vol. 6, no.11, pp. 1665-1671, Nov. 1988.
[ 8] F. Chien and Y. Chan, “Bandwidth enhancement of trans-impedance amplifier by a capacitive-peaking design,” IEEE J. Solid-State Circuits, vol. 34, no. 8, pp. 1167-1170, Aug. 1999.
[ 9] D. Kehrer, H. D. Wohlmuth, H. Knapp, M. Wurzer and A. L. Scholtz, “40-Gb/s 2:1 Multiplexer and 1:2 Demultiplexer in 120-nm Standard CMOS,” IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1830-1837, November 2003.
[20] B. Analui and A. Hajimiri, “Multi-pole bandwidth enhancement technique for transimpedance amplifiers,” ESSCIRC Dig. Tech. Papers, pp. 303-306, Sep. 2002.
[2 ] C. H. Wu, C. H. Lee, W. S. Cheng and S. I. Liu, “CMOS Wideband Amplifiers Using Multiple Inductive-Series Peaking Technique,” IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 548-552, Feb. 2005.
[22] C. Lee, C. H. Wu, and S. I. Liu, “A 1.2V, 18mW, 10Gb/s SiGe Transimpedance Amplifier,” IEEE AP-ASIC, pp. 300-303, Aug. 2004.
[23] F. H. Huang, D. M. Lin, H. P. Wang, W. Y. Chiu and Y. J. Chan, “20 GHz CMOS Injection-Locked Frequency Divider with Variable Division Ratio,” IEEE RFIC, pp. 469 – 472, June 2005.
[24] M. Nogawa, Y. Ohtomo, “A 16.3-GHz 64:1 CMOS FREQUENCY DIVIDER,” IEEE ASICs, pp. 95 – 98, Aug. 2000.
[25] S. Donnay, G. Gielen, editors, “Substrate noise coupling in mixed-signal IC’s,” Kluwer Academic Publishers, 2003.
[26] M. Badaroglu et al., “Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies,” IEEE J. Solid-State Circuits, vol.38, no.7, pp. 1250-1260, Jul. 2003.
[27] M. Xu, D. K. Su, D. K. Shaeffer, T. H. Lee, and B. A. Wooley, “Measuring and modeling the effects of substrate noise on the LNA for a CMOS GPS receiver,” in Proc. IEEE Custom Integrated Circuits Conf., May 2000, pp. 353-356.
[28] D. K. Su, M. J. Loinaz, S. Masui, and B. A. Wooley, “Experimental results and modeling techniques for substrate noise in mixed-signal integrated circuits,” IEEE J. Solid-State Circuits, vol.28, no.4, pp. 420-430, Apr. 1993.
[29] R. Singh, “A review of substrate coupling issues and modeling strategies,” in Proc. IEEE Custom Integrated Circuits Conf., May 1999, pp. 491-499.
[30] T. Blalack, J. Lau, F. J. R. Clement, and B. A. Wooley, “Experimental results and modeling of noise coupling in a lightly doped substrate,” in Int. Electron Devices Meeting Tech. Dig., Dec. 1996, pp. 623-626.
[31] Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, and Maarten Kuijk,” Performance Degradation of LC-Tank VCOs by Impact of Digital Switching Noise in Lightly Doped Substrates,” IEEE J. SOLID-STATE CIRCUITS, VOL. 40, NO. 7, JULY 2005, pp. 1472-1480.
[32] Nisha Checka, David D. Wentzloff, Anantha Chandrakasan, and Rafael Reif, “The effect of substrate noise on VCO performance,” IEEE Radio Frequency Integrated Circuits Symposium, June 2005, pp. 523-525.
[33] B. Razavi , “A study of phase noise in CMOS oscillators,” IEEE J. Solid-State Circuits, vol.31, no.3, pp. 331-343, March 1996.
[34] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high frequency low-power frequency divider,” IEEE J. Solid-State Circuits,pp. 73-76, July. 2004.