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研究生: 葉俊毅
Yeh, Chun-Yi
論文名稱: 應用於可植入式無線腦機介面之資訊樞紐
An Information Hub for Implantable Wireless Brain Machine Interface
指導教授: 馬席彬
Ma, Hsi-Pin
口試委員: 許騰尹
Hsu, Terng-Yin
陳新
Chen, Hsin
黃柏鈞
Huang, Po-Chiun
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2012
畢業學年度: 101
語文別: 英文
論文頁數: 74
中文關鍵詞: 腦機介面生醫系統神經訊號可程式化無損壓縮
外文關鍵詞: Brain Machine Interface, Biomedical System, Neural Signal, Programmable, Lossless Compression
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  • 對於改善大腦受傷或者神經異常的病人而言,腦機介面(Brain-Machine- Interface, BMI)的研究越來越受到矚目,其中最主要的原因,是BMI在高時空解析度下具有可靠刺激與紀錄多個神經細胞活動的能力,而這對神經科學進展來說,也是非常重要的。

    在這篇論文中,我們提出了一個整合多通道紀錄與刺激的腦機介面,並透過電腦或Android系統來與神經細胞做溝通,藉此改善大腦受損或神經異常的病人恢復他們的生理機能。此外,我們以無線傳輸的方式來傳送資料與電源,讓使用者的行動不會受到傳輸線的限制,以增加腦機介面在使用上的便利性。

    而在本篇論文所提出的腦機介面當中,Information Hub扮演著相當重要的腳色。Information Hub根據外部輸入的指令,調整系統的記錄與刺激等各項參數,並產生紀錄與刺激電路所需要的控制訊號來控制個電路的運作。此外,Information Hub亦將記錄到的神經資料作處理,以符合無線傳輸的需求。並進一步對資料做壓縮來節省無線傳輸時的功率消耗,藉由改良過的Lemp-Ziv壓縮法,達到1.8以上的壓縮率,並節省了50%左右的無線傳輸功耗。

    藉由混和訊號SoC的設計流程,並透過TSMC18 1P6M製程,將此腦機介面實作出兩個版本。在第一個版本的晶片當中,晶片面積為3.3 x 2.4 mm2,而Information Hub佔了1.7 x 1 mm2的面積,並且在2 MHz的操作頻率下,有486μW的功率消耗。而在第二版本的晶片當中,進一步改良了硬體消耗,其面積大約為3.06 x 2.53 mm2,而Information Hub佔了2.6 x 0.5 mm2的面積,並且在2 MHz的操作頻率下消耗469μW的功率。


    1 Introduction 1 1.1 Background of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Motivation of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.3 Main Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.4 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 System Description 5 2.1 Introduction of the Implantable Neural Microsystem . . . . . . . . . . . . . 5 2.2 System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2.1 Recording Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.2 Stimulation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.2.3 Wireless Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.4 Information Hub Circuit . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.5 Probe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.6 Intermediate Components . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.7 Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 System Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 System-on-Chip Design of Information Hub for Biomedical Application 15 3.1 Software Design for System Control Mechanism . . . . . . . . . . . . . . . 15 3.1.1 System Operation Flow . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1.2 System Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.1.3 Stimulation Control Mechanism . . . . . . . . . . . . . . . . . . . . 19 3.1.4 Recording Control Mechanism with Power Emergency Solution . . . 19 3.2 Hardware Design for System Implementation . . . . . . . . . . . . . . . . . 21 3.2.1 Hardware Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.2 Microcontroller Improvement . . . . . . . . . . . . . . . . . . . . . 22 3.2.3 Auxiliary Logics Design . . . . . . . . . . . . . . . . . . . . . . . . 25 3.3 System-on-Chip Integration Flow . . . . . . . . . . . . . . . . . . . . . . . 30 4 Lossless Data Compression 33 4.1 Introduction to Data Compression . . . . . . . . . . . . . . . . . . . . . . . 33 4.2 Introduction to Lemp-Ziv Compression . . . . . . . . . . . . . . . . . . . . 35 4.2.1 Variation of Lempel-Ziv Compression . . . . . . . . . . . . . . . . . 37 4.2.2 Software Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 38 4.3 Proposed Modified Lemp-Ziv Compression with Software Simulation . . . . 41 4.4 Combine Proposed Modified Lemp-Ziv Compression with Information Hub . 46 4.4.1 Compression Methodology Implementation . . . . . . . . . . . . . . 46 4.4.2 Software Modification . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.4.3 Hardware Combination . . . . . . . . . . . . . . . . . . . . . . . . . 48 4.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5 Implementation and Integration Results 51 5.1 Mixed-signal System-on-Chip Integration and Co-Verification . . . . . . . . 51 5.2 ASIC Implementation Result . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.2.1 Tape-out Chip Version I . . . . . . . . . . . . . . . . . . . . . . . . 53 5.2.2 Tape-out Chip Version II . . . . . . . . . . . . . . . . . . . . . . . . 56 5.3 System-on-Chip Integration Result . . . . . . . . . . . . . . . . . . . . . . . 59 5.4 SRAM Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 5.5 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6 Conclusion and Future Work 67 6.1 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

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