時間數位轉換器量測電壓脈衝高度之研究｜國立清華大學博碩士論文庫

簡易檢索 / 詳目顯示

回結果列表

研究生：	薛博鴻 Hsueh, Po-Hung
論文名稱：	時間數位轉換器量測電壓脈衝高度之研究
指導教授：	周懷樸 Chou, Hwai-Pwu
口試委員:
學位類別：	碩士 Master
系所名稱：	原子科學院 - 工程與系統科學系 Department of Engineering and System Science
論文出版年：	2009
畢業學年度：	97
語文別：	中文
論文頁數：	65
中文關鍵詞：	時間數位轉換器、延遲鎖相迴路
相關次數：	點閱：2 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

過去十幾年間單斜坡式類比數位轉換器被廣泛的使用在核能科學上，這樣的架構非常適合於低功率多通道的應用上，特別是頻譜測量，但這樣架構的類比數位轉換電路普遍存在著轉換時間過長的缺點。
本研究主題主要針對幅射電壓脈衝高度的量測，提出一單斜坡架構的量測電路，並針對其轉換時間過長的問題加以改善。電路設計使用台積電標準0.18um CMOS製程實現，工作電壓為±1.8V，量測電壓範圍為0∼1.8V，數位信號輸出為12位元，最小時間解析度為78.125ps，晶片面積2.4mm2。

誌  謝 ...................................................I
Abstract ..................................................II
摘  要  .................................................III
目  錄 ..................................................IV
圖目錄 .................................................VII
表目錄 ..................................................X
第1章 緒論 .............................................1
第 2 章 文獻回顧 .........................................3
  2-1單斜坡式類比數位轉換器...............................3
  2-2雙斜坡式類比數位轉換器...............................4
2-3單斜坡雙斜率式類比數位轉換器.........................6
  2-4延遲線...............................................8
第 3 章 電路設計........................................17
　3-1整體架構...........................................18
3-1.1方塊圖..........................................18
    3-1.2量測時序圖......................................20
    3-1.3規格制定........................................21
　3-2電壓-時間轉換電路...................................23
　3-3控制時序產生電路...................................27
  3-4時間量測電路.......................................30
    3-4.1六位元計數器 ...................................30
    3-4.2游標尺延遲線電路 ................ ..............31
    3-4.3延遲元件........................................35
    3-4.4延遲鎖相迴路....................................36
3-4.5電荷幫浦相位偵測器..............................42
3-5讀出電路................................... ........46
3-5.1編碼方式................................ .......46
3-5.2編碼電路................................ .......48
第 4 章 電路模擬與分析..................................53
  4-1電壓時間轉換電路....................... ............53
  4-2游標尺電路.................................... .....54
    4-2.1延遲元件.......................... . ............54
    4-2.2延遲鎖相迴路........................ ...........56
  4-3六位元計數器........................... ............57
  4-4整體電路效能......................... ..............58
  4-5電路佈局............................. ..............61
第 5 章 結論.. ..........................................63
參考文獻.................................................64

                                

[1] O. Saaski, T. Taniguchi, T. K. Ohsaka, H. Mori, T. Nonaka, K. Kaminishi, A. Tsukuda, H. Nishimura, M. Takeda, and Y. Kawakami, “1.2 GHz GaAs Shift Register IC for Dead-Time-Less TDC Application,” IEEE Trans. Nucl. Sci., vol. 36, pp. 512–516, Feb. 1989.
[2] T. Rahkonen, and J. Kostamovaara, “The Use of Stabilized CMOS Delay Line for The Digitization of Short Time Intervals,” IEEE J. Solid-State Circuits, vol. 28, pp. 887–894, Aug. 1993.
[3] C. Ljuslin, J. Christiansen, A. Marchioro, and O. Klingsheim, “An Integrated 16-Channel CMOS Time to Digital Converter,” IEEE Trans. Nucl. Sci., vol. 41, pp. 104–108, Aug. 1994.
[4] J. Christiansen, “An integrated CMOS 0.15 ns Digital Timing Generator for TDC’s and Clock Distribution Systems,” IEEE Trans. Nucl. Sci., vol. 42, pp. 753–757, Aug. 1995.
[5] C. T. Gray, W. Liu, W. A. M. Van Niije, T. A. Hughes Jr., and R. K. Cavin III, “A Sampling Technique and Its CMOS Implementation with 1Gb/s Bandwidth and 25 ps Resolution,” IEEE J. Solid-State Circuits, vol. 29, pp. 340–349, Mar. 1994.
[6] J.-P. Jansson, A. Mantyniemi, and J. Kostamovaara, “A CMOS Time-to-Digital Converter With Better Than 10 ps Single-Shot Precision,” IEEE J. Solid-State Circuits, vol. 41, pp. 1286–1296, Jun. 2006.
[7] A. Mantyniemi, T. Rahkonen, and J. Kostamovaara, “A Nonlinearity-Corrected CMOS Time Digitizer IC With 20 ps Single-Shot Precision,” IEEE International Symposium on Circuits and Systems, ISCAS 2002, Arizona, May 26-29 2002, vol. 1, pp. I-513-I-516, May 2002.
[8] O.B. Milgrome, S.A. Kleinfelder, and M.E. Levi, “A 12 Bit Analog to Digital Converter for VLSI Application in Nuclear Science,” IEEE Trans. Nucl. Sci., vol. 39, pp. 771–775, Aug. 1992.
[9] M.S. Emery, S.S. Frank, C.L. Britton, Jr., A.L. Wintenberg, M.L. Simpson, M.N. Ericson, G.R. Young, L.G. Clonts, and M.D. Allen, “A Multi-Channel ADC for Use in the PHENIX Detector,” IEEE Trans. Nucl. Sci., vol. 44, pp. 374–378, Jun. 1997.
[10] E. Delagnes, D. Breton, F. Lugiez, and R. Rahmanifard, “A Low Power Multi-channel Single Ramp ADC With Up to 3.2 GHz Virtual Clock,” IEEE Trans. Nucl. Sci., vol. 54, pp. 1735–1742, Oct. 2007.
[11] Rudy van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters,” Kluwer Academic Publishers, 2nd ed., ISBN 1-4020-7500-6, 2003
[12] E. Raisanen-Ruotsalainen, T. Rahkonen, and J. Kostamovaara, “An Integrated Time-to-Digital Converter with 30-ps Single-Shot Precision,” IEEE J. Solid-State Circuits, vol. 35, pp. 1507-1510, Oct. 2000.
[13] H.B. Aasnaes and Th.J. Harrison, ‘’Triple Play Speeds A/D Convension,” Electronics, pp. 69-72, April 1968
[14] E. Raisanen-Ruotsalainen, T. Rahkonen, and J. Kostamovaara, “A Low-Power CMOS Time-to-Digital Converter,” IEEE J. Solid-State Circuits, vol. 30, pp. 984-990, Sep. 1995.
[15] M. S. Gobrics, J. Kelly, K.M. Roberts, and R. L. Summer, “A High Resolution Multihit Time to Digital Converter Integrated Circuit,” IEEE Trans. Nucl. Sci., vol. 44, pp. 379–384, Jun. 1997.
[16] T. Fusayasu, “A Fast Integrating ADC Using Precise Time-to-Digital Conversion,” 2007 IEEE Nuclear Science Symposium Conference Record, Oct. 26-Nov. 3, vol. 1, pp. 302–304, Oct. 2007.
[17] P. Dudek, S. Szczepanski, and J.V. Hatfield, “A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line,” IEEE J. Solid-State Circuits, vol. 35, pp. 240-247, Feb. 2000.
[18] C.S. Hwang, P. Chen, and H.W. Tsao, “A High-Precision Time-to-Digital Converter Using a Two-Level Conversion Scheme,” IEEE Trans. Nucl. Sci., vol. 51, pp. 1349–1352, Aug. 2004.

全文公開日期本全文未授權公開 (校內網路)
全文公開日期本全文未授權公開 (校外網路)

簡易檢索 / 詳目顯示

相關論文