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研究生： 林依凡
I-Fan Lin
論文名稱： 以先進電信運算架構為基礎的負載平衡布可夫范紐曼交換機利用DDR SDRAM之緩衝儲存管理器的設計與實作
DDR SDRAM Buffer Management in Advanced TCA Based Load Balanced Birkhoff-von Neumann Switch
指導教授： 李端興
Duan-Shin Lee
口試委員:
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Computer Science
論文出版年： 2008
畢業學年度： 96
語文別： 中文
論文頁數： 87
中文關鍵詞： 交換機 、SDRAM
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    • 負載平衡布可夫范紐曼交換機是個廣為人知可擴充的架構，而且廣為在國際研究社群接受和引用。經證明可以確保100%交換機流量，而且最為人津津樂道的優點，在於這個交換機架構的複雜度很低，不管外界進來的流量為何，是什麼樣的隨機分佈，這個交換機架構都是以它事先定義好的交換機配對様式去作交換，可以得到100%的流量交換保證。正因為有這個低複雜度的獨特優點，所以負載平衡式布可夫馮紐曼網路交換機可以將交換機的規模作到很大。這是放眼目前所有已知的交換機架構所難以望其項背。
    本論文前四章均為介紹此負載平衡布可夫范紐曼交換機的整體架構與設計，包含設計的動機與此交換機的特色以及在實作方面所遇到的問題與解決方案，接下來的第五、六章為學生著重的重點，包含DDR SDRAM的詳細規格定義與操作，以及在此交換機中的緩衝儲存器的設計，如何利用管線化的SDRAM存取設計來達到此系統的嚴格要求。

    摘要 I 序言 II CONTENTS III FIGURES VI CHAPTER 1 MOTIVATION AND INTRODUCTION 1 1.1. INTRODUCTION 2 1.2. OUTLINE OF THE PROPOSAL 3 CHAPTER 2 FEATURES AND INNOVATION OF OUR DESIGN 4 2.1. INHERIT THE BENEFIT FROM LOAD-BALANCED BIRKHOFF-VON NEUMANN SWITCH 4 2.2. FOLDED ARCHITECTURE TO REDUCE CENTRALIZED VOQ BUFFER COMPLEXITY 4 2.3. SWITCHING LEVEL PARALLELISM TO RESTORE 100% THROUGHTPUT 4 2.4. RELIEF OF ORIGINAL SHORT DISTANCE VARIATION CONSTRAINT 5 2.5. 3-LEVEL HIERARCHY VOQ BUFFER DESIGN TO FIT PIPELINE TIMING BUDGET 5 2.6. ADDITIONAL RE-SEQUENCE BUFFER TO SIMPLIFY CELL REASSEMBLY 6 2.7. SYNCHRONIZATION PROTOCOL AND FAULT-TOLERANT SWITCH FABRIC TO PREVENT UNRECOVERABLE REASSEMBLY 6 2.8. PROTOTYPE CREATED BASED ON STANDARD ADVANCEDTCA PLATFORM 7 CHAPTER 3 CHALLENGES AND DESIGN SOLUTION 8 3.1. PRELIMINARY 8 3.1.1. Cell Transmission Time 8 3.1.2. SerDes Channel Latency 10 3.2. CHALLENGES 11 3.2.1. Central VOQ Buffer Complexity Limits Scalability 11 3.2.2. Long Transmission Latency Limits Throughput 11 3.2.3. Synchronization Assumption Restrains Propagation Distance Variation 12 3.2.4. Traditional VOQ Buffer Management Requires Speedup 12 3.2.5. Out-of-Order Transmission Makes Reassembling Difficult 13 3.2.6. Faulty Linecard Makes Permanent Uncoverable Reassembly 13 3.3. DESIGN SOLUTIONS 13 3.3.1. Folded Architecture Design 14 3.3.2. Switching Level Parallelism 17 3.3.3. Synchronization Analysis 19 3.3.4. VOQ Buffer Design 22 3.3.5. Re-sequence Buffer Design 27 3.3.6. Fault Tolerant Design 29 CHAPTER 4 SYSTEM ARCHITECTURE 39 4.1. ASSUMPTION 40 4.2. HARDWARE DESIGN 41 4.2.1. Linecard Blade Design 42 4.2.2. Switch Fabric Blade Design 44 4.2.3. Stand-alone switch integration 45 4.3. SYSTEM OPERATION 47 4.3.1. Ingress Process 47 4.3.2. First Stage Switch 48 4.3.3. VOQ Buffer 49 4.3.4. Second Stage Switch 50 4.3.5. Re-sequencing Buffer 51 4.3.6. Egress Process 52 CHAPTER 5 DDR SDRAM 54 5.1. INTRODUCTION TO DDR SDRAM 54 5.1.1. DDR SDRAM DIMM Overview 54 5.1.2. Initialization 56 5.1.3. Mode Register 57 5.1.4. Read Operation 58 5.1.5. Write Operation 59 5.1.6. DDR SDRAM DIMM Interface and Command Truth Table 60 5.2. PIPELINED READ/WRITE OPERATION 62 5.2.1. Single Bank READ/WRITE Operation 62 5.2.2. Multiple Banks READ/WRITE Operation 64 CHAPTER 6 DESIGN OF BUFFER MANAGER 66 6.1. CONCEPT 66 6.2. PREDEFINED 67 6.2.1. Command Bus 67 6.2.2. Address Bus 68 6.3. CACHE MODULE 68 6.3.1. Cache Load EnQ 70 6.3.2. Cache Retrieve DeQ 72 6.3.3. Access Inserter 74 6.4. SDRAM CONTROLLER MODULE 75 6.4.1. Queue Dispatcher Module 77 6.4.2. Decision Module 79 6.4.3. DIMM CTRL Module 80 CHAPTER 7 CONCLUSION 85 REFERENCES 86

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