研究生: |
林宗儁 Lin, Zsung-Chun |
---|---|
論文名稱: |
低溫複晶矽薄膜電晶體於交流偏壓下劣化之研究 A Study of LTPS TFTs Degradation Under Dynamic Stress |
指導教授: |
金雅琴
King, Ya-Chin |
口試委員: |
盧向成
Lu, S.-C. 林崇榮 Lin, Chrong-Jung |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering |
論文出版年: | 2012 |
畢業學年度: | 101 |
語文別: | 中文 |
論文頁數: | 43 |
中文關鍵詞: | 熱載子效應 、自發熱效應 、低溫複晶矽薄膜電晶體 、可靠度 、動態應力 、交流訊號應力 |
外文關鍵詞: | Hot Carrier Effect, Self-Heating Effect, LTPS TFT, Reliability, Dynamic Stress, AC Stress |
相關次數: | 點閱:3 下載:0 |
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在近幾年來,低溫複晶矽薄膜電晶體,由於其優異的元件特性已經廣泛應用於小型至中型的顯示面板。低溫複晶矽薄膜技術逐漸克服遷移率的問題並提供互補式電路技術,在元件縮小化、面板開口率、功率消耗、畫面品質與解析度上有絕對的優勢。將驅動電路整合於玻璃上,使面板同時具有窄框化(Narrow Frame Size)與高畫質的特性。因此,低溫複晶矽面板是未來的小尺寸顯示裝置的主流。
低溫複晶矽的生命週期是面板技術發的重要關鍵之一,面板的可靠度關係著系統面板的效能,由於周邊驅動電路控制高壓訊號,長期操作於高電壓或高電流的環境,電晶體可靠度的要求更加重要。然而畫素與整合電路的尺寸不斷縮小,將面臨到諸如熱載子效應(Hot Carrier Effect)、自發熱效應(Self-Heating Effect)等可靠度問題。
本研究將討論低溫複晶矽薄膜電晶體在交流訊號操作下的劣化行為,且針對操作在不同溫度、頻率、Duty cycle的情況下,所導致不同的劣化特性,進而分析低溫複晶矽驅動電路的可靠度評估方法修正。
In the last few years Low temperature polycrystalline silicon thin-film transistors, due to it's excellent device characteristics has been widely used in small-to-medium display panel. Recent years, Low temperature polycrystalline silicon thin-film transistors with high carrier mobilities allows for the realization of complementary circuit technology. As device miniaturized, panel aperture ratio, power consumption, the quality and resolution can be further improved. Integrating the driving circuits on the glass, so that the panel also has a narrow frame with higher imaging characteristics. Therefore, low-temperature polycrystalline silicon becomes the mainstream technology for small-to-medium size displays.
The reliability of the panel between the performance of the system panel, peripheral drive circuit is critical to the LTPS technology , Long-term operation in the environment of high voltage or high current ,can greatly affected the transistor’s stability. As the size of transistor is shrinking , devices will experience ever more severe hot carrier effects (Hot Carrier Effect), self-heating effects (Self-Heating Effect) leading to even worse reliability.
This study investigates the degradation behavior of the low temperature polycrystalline silicon thin-film transistors when operate in AC pulse signal. Devices stressed under different temperature, frequency, Duty cycle resulting in different deteriorating characteristics are discussed and analyzed comprehensively.
[1]S. H. Jung, W. J. Nam, and M. K. Han, “A new voltage-modulated AMOLED pixel design compensating for threshold voltage variation in poly-Si TFTs,” IEEE Electron Device Lett., vol.25., NO.10., Oct. 2004, pp. 690-692.
[2]J. H. Oh, H. J. Chung, N. I. Lee, and C. H. Han, “A high-endurance low-temperature polysilicon thin-film transistor EEPROM cell,” IEEE Electron Device Lett.,vol.21.,NO.6.,JUNE 2000, pp. 304.
[3]I.-W.Wu et al.,IEEE Electron Lett.,Vol.12,(1991),pp.181.
[4]A.Pecora et al.,Solid St. Electron,Vol.38,(1995),pp.84.
[5]L.L.Kazmerski,Polycrystalline and Amorphous Thin Films and Devices,(1980),Academic Press.
[6]P.Migliorato et al.,Solid St. Electron,Vol.38,(1995),pp.2075.
[7]J.Fossum et al., IEEE Trans. Electron Devices,Vol.32,No.9,1985,pp.1878.
[8]I.-W Wu et al., IEEE IEDM Tech.Digest,(1990),pp.867.
[9]J. H. Choi, C. S. Kim, B. C. Lim, and J. Jang, “A novel thin film transistor using double amorphous silicon active layer,” IEEE Trans. Electron Devices 45 (1998) 2074.
[10]K. S. Lee, J. H. Choi, S. K. Kim, H. B. Jeon, and J. Jang,“Low off-state leakage current thin-film transistor using Cl incorporated hydrogenated amorphous silicon,” Appl. Phys. Lett., vol. 69, pp. 2403–2405, (1996).
[11]S. K. Kim, K. S. Lee, J. H. Choi, C. S. Kim, and J. Jang,“High performance a-Si : H(: Cl) TFT,” in Proc. Electrochem. Soc., (1996), vol. 96–23, pp. 138–145.
[12]Y. J. Choi, B. C. Lim, I. K. Woo, J. I. Ryu, and J. Jan,“Low photo-leakage current amorphous silicon thin fillm transistor with a thin active layer,” J. Non-Cryst. Solids 266 (2000) 1299.
[13]D.B. Thomasson, T.N. Jackson, IEEE Electron Device Lett. 18 (1997) 397.
[14]J.E. Lan, T.K. Chou, C.S. Chiang, J. Kanicki, Mater. Res. Soc. Symp. Proc. 471 (1997) 27.
[15]N. Hirano, N. Ikeda, H. Yamaguchi, S. Nishida, Y. Hirai, and S. Kaneko, IDRC ’94 Digest, International Display Research Conference, CA, 1994 (unpublished), p. 369.
[16]H. Y. Lu, T. C. Chang, P. T. Liu, H. W. Li, C. W. Hu, K. C. Lin, C. C. Wang, Y. H. Tai, and S. Chi, “Reduction of photoleakage current in polycrystalline silicon thin-film transistor using NH3 plasma treatment on buffer layer,” Appl. Phys. Lett. 92, 153507 (2008).
[17]K. Suzuki, F. Takeuchi, Y. Ebiko, M. Chida, and N. Sasaki, Tech. Dig. -Int. Electron Devices Meet. 2004, 785.
[18]H. Y. Lu, T. C. Chang, P. T. Liu, H. W. Li, C. W. Hu, K. C. Lin, Y. H. Tai, Y. H. Tai, and S. Chi, “Elimination of photoleakage current in poly-Si TFT using a metal-shielding structure,” Electrochemical and Solid-State Letters, 11(5) J34-J36 (2008).
[19]H.L.Chen et al.,IEEE Trans. Electron Devices,Vol.46,No.4,(1999),pp.722
[20]S.Inoue,et al.,IEEE IEDM Tech.Digest,(1996),pp.781
[21]L.T.Su et al.,IEEE International Electron Devices Meeting,(1992),pp.357.
[22]T.Motai,Int'l.Workshop on AMLCD,(1999),pp.271.
[23]H. H. Lin , Study of LTPS TFTs Degradation under Gate Pulse Stress in OFF Region with Drain Bias Study of LTPS TFTs Degradation under Gate Pulse Stress in OFF Region with Drain Bias,(2007)