此論文提出了三項與振盪器有關的技術，應用於機體射頻系統，並且將這
些技術實踐於四個COMS晶片。
第一項是應用於駐波振盪器陣列的直接偶和技術：在振盪器陣列中，每個
單元的振盪電流經由共振腔，直接注入至相鄰的單元。此論文使用此技
術，呈現了兩個二維駐波振盪器陣列。第一個陣列可於晶片中多個位置，
提供相同頻率、振幅和相位的同步訊號，此陣列震盪頻率為61.5GHz，
使用90nm CMOS製程。為了透過無線量測驗證其同步性，同個一晶片
中整合了，包括二維駐波振盪器陣列、射頻驅動器陣列和環狀天線的毫米
波輻射器。透過無線量測得到1x1、2x2和3x3的有效全向輻射功率和相
位雜訊，並觀察其關係，可得到同步性的間接證據。在陣列法向方位的有
效全向輻射功率以10logN^2的倍數成長，並且相位雜訊以10logN的倍
數遞減，其中N代表陣列中的單元數量。第二個駐波振盪器陣列則可於晶
片中多個位置，提供相同頻率和振幅但多相位的同步訊號，此陣列震盪
基頻為312.5GHz，使用65nm CMOS製程，此陣列是設計用於二維兩倍
諧波(265GHz)的空間功率輻射與結合。
第二項技術實現於一個65nm CMOS太赫茲天線陣列接收器。此接收
器為一個兩次轉換差外插架構，第一次降頻由一個字鎮三倍諧波混
波器前端來完成，而第二次降頻則由一個Gilbert-cell混波器和本地
振盪器來達成，此接受器還與一個四單元的環狀天線陣列共同設計
和積體化。312GHz的射頻輸入訊與96.1GHz本地振盪器的三倍諧波
混頻，產生23.8GHz的第一個中頻，而第二個本地振盪器頻率為22.3
GHz，所以產生的第二個中頻為1.5 GHz。
在最後一個晶片中，呈現一個用於本地振盪器相位雜訊之射頻內建自我測
試平台的分析、設計和實踐。此平台中，一個注入鎖定振盪器相位鑑別器
與一個2.56GHz的鎖相迴路被整合於65nm CMOS製程。此射頻內建自我測試頻台所產生的相位雜訊量測結果，與信號源分析儀的量測結果
相比，在100kHz、1MHz和10MHz位移頻率的誤差分別為0.9 dB、1.2
dB和2.6 dB。

In this dissertation, three techniques in relation to oscillators are proposed for integrated RF system. Four chips are implemented in CMOS based these techniques.
First of all, a direct-coupled technique for standing wave oscillator (SWO) arrays is presented. The oscillation currents of a unit cell in the SWO array directly inject to adjacent cells through the resonator. Two 2-D SWO arrays based on the technique are reported. The first one can provide synchronous signals with identical frequencies, amplitudes, and phases at multiple locations over a chip. It is implemented in a 90-nm CMOS technology with 61.5-GHz oscillation frequency. Millimeter-wave radiators that consists of the proposed 2-D SWO array, an RF driver array, and an on-chip loop antenna array are implemented in a single chip to verify the synchronicity via wireless measurement. The indirect evidence of synchronicity is provided from the correlation between the wireless measured effective isotropic radiated power (EIRP) and phase noise of 1x1, 2x2, and 3x3 arrays. The EIRP in the normal direction of the array is increasing by a factor of 10logN^2 and the phase noise is reducing by a factor 10logN of over that of a single cell, where N is the number of unit cells in the array. The second SWO array can provide synchronous signals with identical frequencies, amplitudes, and multiple phases at multiple locations over a chip. It is implemented in a 65-nm CMOS technology with 132.5-GHz fundamental frequency. The SWO array is designed for 2-D second harmonic (265-GHz) spatial power radiating and combining.
The second technique is realized in a THz antenna array receiver in 65-nm CMOS. The receiver is a double-conversion superheterodyne architecture. The first down-conversion is accomplished by a self-oscillating 3X subharmonic mixer frontend, and the second down-conversion is performed by a Gilbert-cell mixer and a local oscillator. The receiver is co-designed and integrated with a 4-element loop antenna array. By mixing an RF input signal at 312 GHz with the third harmonic of the 96.1GHz LO, the first IF of 23.8 GHz is produced. The second LO is at frequency of 22.3 GHz,
and the second IF is 1.5 GHz.
An RF built-in self-test (BIST) bench on local oscillator phase noise is presented in the last work. An injection-locked-oscillator phase discriminator integrated with a 2.56-GHz phase-locked loop in a 65-nm CMOS technology is proposed in this bench. In comparison with a signal source
analyzer, the RF-BIST bench provides the phase noise profile with 0.9-dB, 1.2-dB, and 2.6-dB errors at 100-kHz, 1-MHz, and 10-MHz offset frequencies respectively.

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