隨著現今技術的發展，高靈敏度光偵測器的需求日益增加，推動了單光子偵測技術的進步。目前單光子雪崩崩潰二極體（Single Photon Avalanche Diode, SPAD）是最常見的單光子偵測器之一，原理是將二極體逆偏壓至崩潰電壓以上，利用接面空乏區內的載子進行碰撞游離化（Impact Ionization）來瞬間產生極大光電流，搭配冷卻電路進行蓋格模式偵測。缺點是Si-based SPAD通常需要十幾伏特以上的操作電壓，系統必須額外搭配升壓（Boost Converter）與降壓（Buck Converter）電路來提供此高電壓，提高了系統的複雜度與功耗。因此本研究的目的在於找出標準CMOS製程中之雙極性電晶體結構並利用電晶體本身的內部增益降低崩潰電壓，以此來當作單光子雪崩崩潰電晶體（Single Photon Avalanche Transistor, SPAT）並且研究其崩潰的機制。
本研究使用TSMC 0.18μm標準 CMOS 製程來設計新型單光子雪崩崩潰電晶體。總共有兩個大方向，一為寄生橫向雙極性電晶體，一為縱向雙極性電晶體，透過雙極性電晶體（Bipolar Junction Transistor, BJT）基極浮接，使電洞累積於基極並抬升基極電位，使基射極接面處於順偏，讓大量電子能夠從射極注入至集極，降低集極與射極間的崩潰電壓(BV_ceo)。
透過元件模擬進一步分析所提出之光電晶體，分析崩潰時的物理機制。並設計多種不同結構的光電晶體，找出結構與崩潰電壓之間的關係，並盡量降低崩潰電壓，使整體電路的功耗能夠更低。

With the advancement of modern technology, the demand for high-sensitivity optical detectors has been increasing, driving progress in single-photon detection technology. Among these, the Single Photon Avalanche Diode (SPAD) is one of the most commonly used single-photon detectors. Its principle involves reverse-biasing the diode beyond its breakdown voltage, utilizing carrier impact ionization in the depletion region to generate a large avalanche photocurrent instantaneously, which is then detected in Geiger mode with the aid of cooling circuits. However, a major drawback of Si-based SPADs is that they typically require an operating voltage of several tens of volts. This necessitates additional boost and buck converter circuits to supply the required high voltage, increasing system complexity and power consumption.
This study aims to identify bipolar transistor structures within a standard CMOS process and leverage the internal gain of the transistor to reduce the breakdown voltage. By doing so, we propose a Single Photon Avalanche Transistor (SPAT) and investigate its breakdown mechanisms.
A novel SPAT is designed using the TSMC 0.18 μm standard CMOS process. Two main approaches are explored: parasitic lateral bipolar junction transistors (LBJT) and vertical BJTs(VBJT). By floating the base terminal of the BJT, hole accumulation in the base region raises the base potential, forward-biasing the base-emitter junction. This facilitates electron injection from the emitter to the collector, thereby reducing the collector-emitter breakdown voltage (BV_ceo).
Through device simulations, we further analyze the proposed phototransistor and examine the underlying physical mechanisms of breakdown. Various structural designs of the phototransistor are investigated to establish the relationship between device structure and breakdown voltage, with the goal of minimizing the breakdown voltage and reducing overall circuit power consumption.

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