近年來，生醫電子的發展越來越受到重視，特別是可攜式生理即時監測系統的相關產業更是蓬勃發展。配合攜帶型裝置的需求，低功耗、小體積成了這些系統中電路必然的發展趨勢。針對生醫訊號擷取系統，本論文提出10位元、1.28MS/s的連續漸近式類比至數位轉換器(SAR ADC)。其以單向式三級參考位準切換式電容陣列作為電路中的數位至類比轉換器(DAC)，其電容切換能量消耗及單位電容使用數僅為傳統式切換DAC的9.5%及25%。所設計之SAR ADC以TSMC 90nm CMOS製程實現，晶片總面積為1mm2而核心電路面積為0.205 mm2。在0.7V、1.28MS/s的量測下，SAR ADC的DNL為5.312/-1 LSB、INL為6.559/-3.932 LSB；在動態效能方面，SFDR為56.51dB、SNDR為47.13dB，而ENOB為7.53位元。其功率消耗為9.44uW，所達到之價值指標(FOM)為39.9fJ/conversion-step。為了有更好的效能，本論文另提出一10位元的SAR ADC，並同樣以TSMC 90nm CMOS製程實現，其DAC改以交替式三級參考位準切換式電容陣列實現，在電容數量不變的情況下，其平均電容切換能量消耗為傳統式切換DAC的13.5%，同時搭配可調偏移式比較器，以改善因DAC的不對稱切換所引發的動態偏移效應。此SAR ADC的晶片總面積為1mm2、核心電路面積則為0.14025mm2。在0.5V、1.28MS/s下，SAR ADC的量測DNL為0.646/-0.929 LSB、INL為1.556/-1.467 LSB；SFDR、SNDR及ENOB也分別提升至60.21dB、50.78dB、8.14位元。而此SAR ADC的平均功率消耗為4uW，FOM則改善為11.078 fJ/conversion-step。

In recent years, the industry of the portable electronic devices for bio-medical signals monitoring has been significantly growing. For the requirement of these portable devices, low power dissipation and high hardware efficiency are the main goals of the circuit design for the bio-medical electronics.
A 10-bit, 1.28MS/s successive approximation register analog-to-digital converter (SAR ADC) for the acquisition system of bio-medical signals is presented in this thesis. In this SAR ADC, the DAC is functioned by a tri-level monotonic switching capacitive architecture. Its average switching energy is 9.5% to that of conventional switching capacitive DAC (CDAC), while its capacitor amount is 25% to that of conventional switching CDAC. The SAR ADC was fabricated in TSMC 90nm CMOS technology. The whole chip area was 1mm2, while the core circuit area was 0.205mm2. At 0.7V and 1.28MS/s, the static experimental performance of this SAR ADC were DNL of 5.312/-1 LSB and INL of 6.559/-3.932 LSB; the dynamic experimental performance were SFDR of 56.51dB, SNDR of 47.13dB, and ENOB of 7.53 bit. The SAR ADC dissipated power of 9.44uW, and achieved FOM of 39.9fJ/conversion-step.
For better performance, another 10-bit SAR ADC is presented and also fabricated in TSMC 90nm CMOS technology. To lessen the dynamic offset effect induced by asymmetric switching process of monotonic switching CDAC, the improved SAR ADC was formed by an offset adjustable comparator and a proposed tri-level alternative switching CDAC. The average switching energy of this CDAC was 13.5% to that of conventional switching CDAC. The whole chip area was 1mm2, while the core circuit area was 0.14025mm2. At experiment conditions of 0.5V and 1.28MS/s, this SAR ADC had DNL of 0.646/-0.929 LSB, INL of 1.556/-1.467 LSB, and its SFDR, SNDR, and ENOB were enhanced to 60.21dB, 50.78dB, and 8.14 bit, respectively. The power dissipation of this SAR ADC was 4uW, and the resulting FOM was improved to 11.078 fJ/conversion-step.

[1] Jack E Brown-Telcom Professional, Medical Body Area Network’s,
http://jackbrowntelecomprofessional.wordpress.com/
[2] R. Martins, S. Selberherr, and F.A. Vaz, “A CMOS IC for portable EEG acquisition systems,” IEEE Trans. Instrum. Meas., vol. 47, no.5, pp. 1191-1196, Oct, 1998.
[3] H.-J. Yoo and C.V. Hoof, Bio-Medical CMOS ICs Integrated Circuits and Systems, Springer, 2011.
[4] K. A. Ng, P.K. Chan, “A CMOS analog front-end IC for portable EEG/ECG monitoring applications,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 52, no. 11, pp. 2335-2347, Nov. 2005.
[5] H.Y. Yang, R. Sarpeshkar, “A bio-inspired ultra-energy-efficient analog-to-digital converter for biomedical applications,” IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 53, no. 11, pp. 2349-2356, Nov. 2006.
[6] Behzad Razavi, Principle of Data Conversion System Design, AT&T Bell Laboratories, 1995.
[7] D. Johns and K. Martin, Analog Integrated Circuit Design. NewYork: John Wiley & Sons, Inc., 1997.
[8] Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001.
[9] J. McCreary and P. Gray, “All-MOS charge redistribution analog-to-digital conversion techniques. I,” IEEE J. Solid-State Circuits, vol. 10, no. 6, pp. 371-379, Dec. 1975.
[10] R. Suarez, P. Gray, and D. Hodges, “All-MOS charge redistribution analog-to-digital conversion techniques. II,” IEEE J. Solid-State Circuits, vol. 10, no. 6, pp. 379-385, Dec. 1975.
[11] Tan Kuo Hwi Roy and T. Teo,” A 0.9V 100nW rail-to-rail SAR ADC for biomedical applications,” in IEEE Int. Symp. on Integrated Circuits (ISIC), Sep. 2007, pp. 481-484.
[12] Y.-K. Chang, C.-S. Wang, and C.-K. Wang,” A 8-bit 500-KS/s low power SAR ADC for bio-medical applications,” in IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2007, pp. 228-231.
[13] W.-Y. Pang, C.-S. Wang, Y.-K. Chang, N.-K. Chou, and C.-K. Wang, “A 10-bit 500-KS/s low power SAR ADC with splitting comparator for bio-medical applications,” in IEEE Asian Solid-State Circuits Conference (ASSCC), Nov. 2009, pp. 149-152.
[14] S. Gambini and J. Rabaey, “Low-power successive approximation converter with 0.5V supply in 90nm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2348-2356, Nov. 2007.
[15] B. Ginsburg and A. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739-747, Apr. 2007.
[16] A.M. Abo and P.R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.
[17] Hao-Chiao Hong, and Guo-Ming Lee, “A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2161-2168, Oct. 2007.
[18] T.B. Cho, and P.R. Gray, “A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,” IEEE J. Solid State Circuits, vol. 30, no. 3, pp. 166-172, Mar. 1995
[19] A.S. Sedra, and K.C. Smith, Microelectronic Circuits, New York: Oxford Universiy Press, 2004.
[20] P.E. Allen, and D.R. Holberg, CMOS Analog Circuit Design, 2nd ed., Oxford University Press, 2002.
[21] B. Ginsburg and A. Chandrakasan, “An energy-efficient charge recycling approach for a SAR converter with capacitive DAC,” in Proc. IEEE Int. Symp. Circuits and System (ISCAS), May 2005, pp. 184-187.
[22] J.-S. Lee and I.-C. Park, “Capacitor array structure and switch control for energy-efficient SAR analog-to-digital converters,” in Proc. IEEE Int. Symp. Circuits and System (ISCAS), May 2008, pp. 236-239.
[23] Y. Lee and I.-C. Park, “Capacitor array structure and switching control scheme to reduce capacitor mismatch effects for SAR analog-to-digital converters,” in Proc. IEEE Int. Symp. Circuits and System (ISCAS), May 2009, pp. 1464-1467
[24] S.-W.M. Chen and R. Brodersen, “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-m CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006.
[25] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13 m CMOS process,” in IEEE Symp. VLSI Circuits Dig., Jan. 2009, pp. 236-237.
[26] C.-C. Liu, S.-J. Chang, G.-Y. Huang, and Y.-Z. Lin, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010.
[27] G.-Y. Huang, S.-J. Chang, C.-C. Liu, and Y.-Z. Lin, “10-bit 30MS/s SAR ADC using a switchback switching method,” IEEE Transation on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 3, pp. 584-588, Mar. 2013.
[28] Y. Zhu, C.-H. Chan, U-F. Chio, S.-W. Sin, S.-P. U, R.P. Martins, and F. Maloberti, “A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, Jun. 2010.
[29] V. Hariprasath, J. Guerber, S.-H. Lee, and U.-K. Moon, “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” Electron. Lett., vol. 46, no. 9, pp. 620-621, Apr. 2010.
[30] B. Razavi and B.A. Wooley, “Design technique for high-speed high-resolution comparator,” IEEE J. Solid-State Circuits, vol. SC-27, pp. 1916-1926, Dec. 1992.
[31] C.-H. Chan, Y. Zhu, U-F. Chio, S.-W. Sin, S.-P. U, and R.P. Martins, “A voltage-controlled capacitance offset calibration technique for high resolution dynamic comparator,” in IEEE Int. SoC Design Conference (ISOCC), Nov. 2009, pp. 392-395.
[32] S.-K. Lee, S.-J. Park, H.-J. Park, and J.-Y. Sim, “A 21fJ/conversion-step 100kS/s 10-bit ADC with a low-noise time-domain comparator for low-power sensor interface,” IEEE J. Solid-State Circuits, vol. 46, no. 3, pp. 651-659, Mar. 2011.
[33] Z. Zeng. C.-S. Dong, and X. Tan, “A 10-bit 1MS/s low power SAR ADC for RSSI application,” in IEEE Int. Conf. on Solid-State and Integrated Circuit Technology (ICSICT), Nov. 2010, pp. 569-571.
[34] M. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 10-bit charge-redistribution ADC consuming 1.9 W at 1MS/s,” IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1007-1016, May 2010.
[35] T.G.R. Kuntz, C.R. Rodrigues, and S. Nooshabadi, “An energy-efficient 1MSps 7W 11.9fJ/conversion step 7pJ/sample 10-bit SAR ADC in 90nm, ” in Proc. IEEE Int. Symp. Circuits and System (ISCAS), May 2011, pp. 261-264.
[36] G. Yin, U-F. Chio, H.-G. Wei, S.-W. Sin, S.-P. U, R.P. Martins, and Z. Wang, “An ultra low power 9-bit 1-MS/s pipelined SAR ADC for bio-medical applications,” in IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec. 2010, pp. 878-881.
[37] T. Rabuske, J. Fernandes, S. Nooshabadi, C. Rodrigues, and F. Rabuske, “A 749nW 1MSps 8-bit SAR ADC at 0.5V employing boosted switches,” in IEEE International Conference on Electronics, Circuits and Systems (ICECS), Dec. 2012, pp. 500-503.
[38] A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR ADC with tri-level comparator in 40nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 4, pp. 1022-1030, Apr. 2012.
[39] C.-Y. Liou, and Chih-Cheng Hsieh, “A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2013, pp. 280-281.
[40] K. Yoshioka, A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with wide range threshold configuring comparator,” in Proc. Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2012, pp. 381-384.
[41] K. Laker and W. Sansen, Design of Analog Integrated Cricuits and Systems. New York, NY: McGraw-Hill, 1994.