「電路的冗餘添加和移除」和「基於自動測試樣本產生/診斷的設計重新繞線」這兩種技術都是用於邏輯設計電路中的合成和優化的重組技術。「電路的冗餘添加和移除」技術先加入一些冗餘的電路線，導致可以移除要刪除的目標電路線；而「基於自動測試樣本產生/診斷的設計重新繞線」的技術先加入一些錯誤(也就是移除目標電路線)，然後修正這個錯誤的電路，使得電路功能沒有受到改變。「基於自動測試樣本產生/診斷的設計重新繞線」的技術是一個完整的演算法，透過跑診斷和自動測試樣本產生演算法，且提供一個比「電路的冗餘添加和移除」還廣泛的邏輯電路重組，然而這種技術有個缺點，必須在電路重組後做驗證的動來確保電路的正確性。因此，這篇論文提出一個新的電路重組技術「錯誤引入與修正」，透過正規的方法來建立修正電路，修正因為移除電路線所造成的錯誤。因為「錯誤引入與修正」沒有使用自動測試樣本產生和驗證的程序，和「基於自動測試樣本產生/診斷的設計重新繞線」相比可改善執行時間，但可能會犧牲一些重組的結果。「錯誤引入與修正」同時可以處理任意加電路線和置換邏輯閘的錯誤已達到更廣泛的電路重組。

Redundancy Addition and Removal (RAR) and ATPG/Diagnosis-based Design Rewiring (ADDR) are both restructuring techniques used in the synthesis and optimization of logic designs. The RAR adds some redundant wires or gates to the circuit and results in the removal of target wires while the ADDR injects some errors (i.e., removes target wires) and corrects them to make the functionality of the circuit intact. The ADDR is a complete rewiring algorithm by running diagnosis and ATPG algorithms, and provides a wide variety of logic transformations than RAR does. The necessity of verification for validating the restructuring operation, however, is a drawback in the ADDR algorithm. Thus, this paper proposes a novel restructuring technique, Error Injection and Correction (EIC), which formally constructs a corresponding rectification network to the error due to the target wire removal. Since the EIC does not involve diagnosis and ATPG/verification processes, it could improve the run time as compared with ADDR in theory at the expense of missing some restructuring potential. The EIC is also extended to deal with additional types of restructuring operations, including wire addition and gate replacement for achieving more diverse circuit restructuring.

[1] M. S. Abadir, J. Ferguson and T. E. Kirkland, "Logic Design Verification via Test Generation," IEEE Trans. Computer-Aided Design, vol. 7, pp. 138-148, Jan. 1988.
[2] Berkeley Logic Synthesis and Verification Group, "ABC: A System for Sequential Synthesis and Verification," http://www.eecs.berkeley.edu/~alanmi/abc/
[3] C.-W. Jim Chang, M.-F. Hsiao, and M. Marek-Sadowska, "A New Reasoning Scheme for Efficient Redundancy Addition and Removal," IEEE Trans. Computer-Aided Design, vol. 22, pp. 945-952, July 2003.
[4] S.-C. Chang, K.-T. Cheng, N.-S Woo, and M. Marek Sadowska, "Postlayout Logic Restructuring Using Alternative Wires," IEEE Trans. Computer-Aided Design, vol. 16, pp. 587-596, June 1997.
[5] S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, "Perturb and Simplify: Multi-level Boolean Network Optimizer," IEEE Trans. Computer-Aided Design, vol. 15, pp. 1494-1504, Dec. 1996.
[6] S.-C. Chang, L. P. P. P. Van Ginneken, and M. Marek-Sadowska, "Fast Boolean Optimization by Rewiring," in Proc. Int. Conf. Computer-Aided Design, 1996, pp. 262-269.
[7] Y.-C. Chen and C.-Y. Wang, "An Improved Approach for Alternative Wires Identification," in Proc. Int. Conf. Computer Design, 2005, pp. 711-716.
[8] Y.-C. Chen and C.-Y. Wang, "Fast Detection of Node Mergers Using Logic Implications," in Proc. Int. Conf. on Computer-Aided Design, 2009, pp.785-788.
[9] Y.-C. Chen and C.-Y. Wang, "Node Addition and Removal in the Presence of Don't Cares ,"in Proc. Design Automation Conf., 2010, pp. 505-510.
[10] S.-C. Fu, T.-K. Lam, and Y.-L. Wu, "On Improved Scheme for Digital Circuit Rewiring and Application on Further Improving FPGA Technology Mapping," in Proc. Asia and South Pacific Design Automation Conf., 2009, pp.197-202.
[11] T. Kirkland and M. R. Mercer, "A Topological Search Algorithm for ATPG," in Proc. Design Automation Conf., 1987, pp. 502-508.
[12] A. Kuehlmann, "Dynamic Transition Relation Simplification for Bounded Property Checking," in Proc. Int. Conf. on Computer-Aided Design, 2004, pp. 50-57.
[13] W. Kunz and D. K. Pradhan, "Recursive Learning: A New Implication Technique for Efficient Solutions to CAD Problems-Test, Verification, and Optimization," IEEE Trans. Computer-Aided Design, vol. 13, pp. 1143-1158, Sep. 1994.
[14] C.-C. Lin and C.-Y. Wang, "Rewiring Using IRredundancy Removal and Addition," in Proc. Design, Automation and Test in Europe, 2009, pp. 324-327.
[15] W.-H. Lo and Y.-L.Wu, "Improving Single-Pass Redundancy Addition and Removal with Inconsistent Assignments," in Proc. Int. Symp. on VLSI Design, Automation
and Test, 2006, pp. 175-178.
[16] A. Mishchenko, S. Chatterjee, and R. Brayton, "DAG-Aware AIG Rewriting: A Fresh Look at Combinational Logic Synthesis," in Proc. Design Automation Conf., 2006, pp. 532-536.
[17] M. H. Schulz and E. Auth, "Advanced Automatic Test Pattern Generation and Redundancy Identification Techniques," in Proc. Int. Fault-Tolerant Computing Symp.,
1988, pp. 30-35.
[18] W.-C. Tang, W.-H. Lo, T.-K. Lam, K.-K. Mok, C.-K. Ho, S.-H. Yeung, H.-B. Fan, and Y.-L. Wu, "A Quantitative Comparison and Analysis on Rewiring Techniques," in Proc. Int. Conf. on ASIC, 2003, pp. 242-245.
[19] A. Veneris and M. S. Abadir, "Design Rewiring Using ATPG," IEEE Trans. Computer-Aided Design, vol. 21, pp.1469-1479, Dec. 2002.
[20] A. Veneris and I. N. Hajj, "Design Error Diagnosis and Correction via Test Vector Simulation," IEEE Trans. Computer-Aided Design, vol. 18, pp. 1803-1816, Dec.1999.
[21] Y.-L.Wu, W.-N. Long, and H.-B. Fan, "A Fast Graph-based Alternative Wiring Scheme for Boolean Networks," in Proc. Int. VLSI Design Conf., 2000, pp. 268-273.
[22] X.-Q. Yang, T.-K. Lam, and Y.-L. Wu, "ECR:A Low Complexity Generalized Error Cancellation Rewiring Scheme," in Proc. Design Automation Conf., 2010, pp. 511-516.