非晶相氧化物半導體(Amorphous Oxide Semiconductors: AOSs)由於具有可低溫沉積、可撓曲、透明性以及均勻度佳等特點，受到廣泛的重視。目前被研究的氧化物半導體有ITO、IZO、TiO2、ZnO、In2O3、Ga2O3、IGO、a-IGZO等。其中以非晶相銦鎵鋅氧化物(Amorphous InGaZnO: a-IGZO)薄膜當作主動層(Active layer)的薄膜電晶體(Thin Film Transistors: TFTs)，載子遷移率與可靠度比傳統氫化非晶矽薄膜電晶體(a-Si:H TFT)高、均勻性優於低溫複晶矽薄膜電晶體(Low Temperature Polycrystalline Silicon TFT: LTPS TFT) 且可低溫製程，因此a-IGZO薄膜電晶體具有取代氫化非晶矽薄膜電晶體與低溫複晶矽薄膜電晶體來製作主動矩陣有機發光顯示器(Active Matrix Organic Light Emitting Display: AMOLED)的潛力。由於a-IGZO材料的載子濃度可經由製程條件以及後續處理來控制，使a-IGZO材料形成導體、半導體或絕緣體特性，因此a-IGZO薄膜其另一項具革命的技術發展為幫助系統面板(System on Panel: SOP)的實現；即是將所有的周邊電路，關鍵元件，記憶體元件，驅動電路等，全部整合於玻璃基板上。其中非揮發性記憶體元件(Nonvolatile Memory: NVM)是實現系統面板的關鍵零組件之一。因此本論文以a-IGZO薄膜為電荷儲存層(Charge Storage Layer)的非揮發性記憶體，製作出鋁/氧化矽/a-IGZO/氧化矽/矽(MOIOS)的記憶體結構。研究a-IGZO非揮發性記憶體在未退火處理、300℃退火處理以及NH3電漿處理下，對資料寫入(Program)、抹除(Erase)、耐操度(Endurance)與資料保存特性(Retention)的影響。實驗結果指出， 以a-IGZO薄膜為電荷儲存層的非揮發性記憶體具有好的記憶體特性。而高溫使a-IGZO薄膜由絕緣體特性轉變成導體特性，導致a-IGZO非揮發性記憶體在300℃退火處理或NH3電漿處理下具有較差的記憶體特性。

Amorphous oxide semiconductors (AOSs) are attracted much attention due to low temperature deposition, flexible, transmission, and uniformity. It has been investigated of AOSs, such as ITO, IZO, TiO2, ZnO, In2O3, Ga2O3, IGO, a-IGZO, etc. Especially, the thin film transistors (TFTs) with a-IGZO thin film as active layer perform higher mobility and better reliability than conventional hydrogenated amorphous silicon TFT (a-Si: H TFT). However, the uniformity of a-IGZO TFT is superior to Low Temperature Polycrystalline Silicon TFT (LTPS TFT). In addition, the a-IGZO thin film can fabricate at low temperature. Therefore, the a-IGZO TFTs have the potential to replace a-Si: H TFT and LTPS TFT forming Active Matrix Organic Light Emitting Display (AMOLED). Because we can control the carrier concentration of a-IGZO thin film by different process conditions and post treatments, it can form one of three types such as conductor, semiconductor, and insulator. Another breakthrough technology of a-IGZO TFT is to achieve system on panel (SOP). This means that periphery circuits, key devices, driving circuits and memory all integrated on glass substrate. The system nonvolatile memory (NVM) is the key component to realize the system on panel. The thesis studies that NVM employing a-IGZO as charge trapping layer to fabricate the structure forming Al/Oxide/a-IGZO/Oxide/Si (MOIOS). Investigate the effect of memory properties such as program, erase, endurance, and data retention at not annealing, 300oC annealing, or NH3 plasma treatment. The result shows that NVM with a-IGZO as charge trapping layer has good memory property. However, the a-IGZO thin film transfers from conductor characteristic to insulator characteristic result in worse memory property at 300oC annealing or NH3 plasma treatment.

Chapter 1
[1.1] K. Jain, M. Klosner, M. Zemel, S. Raghunandan, “Flexible Electronics and Displays: High-Resolution, Roll-to-Roll, Projection Lithography and Photoablation Processing Technologies for High-Throughput Production,” Proceedings of The IEEE, vol. 93, pp. 1500-1510, 2005.
[1.2] H. N. Lee, J. Kyung. M. C. Sung, et al., “Oxide TFT with multilayer gate insulator for backplane of AMOLED device,” Journal of the SID, 16/2, 2008.
[1.3] M. Ito, M. Kon, C. Miyazaki, et al. “Amorphous oxide TFT and their applications in electrophoretic displays,” Phys. Stat. Sol. (a), 205, No. 8, pp. 1885–1894, 2008.
[1.4] H. Hosono, “Ionic amorphous oxide semiconductors: Material design, carrier transport, and device application,” Journal of Non-Crystalline Solids, 352, pp. 851-858, 2006.
[1.5] M. J. Powell, C. V. Berkel, I. D. French, et al., “Bias dependence of instability mechanisms in amorphous silicon thin-film transisors,” Applied Physics Letters, vol. 51, pp. 1242-1244, 1987.
[1.6] P. Migliorato, C. Reita, G. Tallatida, M. Quinn and G. Fortunato, “Anomalous off-current mechanisms in n-channel poly-Si thin film transistors.” Solid State Electronics, vol. 38, pp. 2075-2079, Aug. 1995.
[1.7] M. Hack, I-W. Wu, T. H. King and A. G. Lewis, “Analysis of Leakage Currents in Poly-silicon Thin Film Transistors,” IEEE Int. Electron Devices Meeting Tech. Dig., pp. 385-387, 1993.
[1.8] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este, and M. Rider, “Conductivity behavior in polycrystalline semiconductor thin film transistors,” J. Appl. Phys. vol. 53, pp.1193-1202, 1982.
[1.9] N. Yamauchi, J. J. Hajjar and R. Reif, “Drastically improved performance in poly-Si TFTs with channel dimensions comparable to grain size,” IEEE Int. Electron Devices Meeting Tech. Dig., pp. 353 - 356, 1989.
[1.10] P. F. Carcia, R. S. McLean, M. H. Reilly, and G. Nunes, “Transparent ZnO thin-film transistor fabricated by rf magnetron sputtering,” Applied Physics Letters, vol. 82, pp. 1117-1119, 2003.
[1.11] R. E. Presley, C. L. Munsee, C. –H. Park, D. Hong, J. F. Wager, and D. A. Keszler, “Tin oxide transparent thin-film transistors,” J. Phys. D., 37, 2810, 2004.
[1.12] K. Nomura, H. Ohta, A. Takagi, et al., “Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductor,” Nature, vol. 432, pp. 488-492, 2004.
[1.13] K. Nomura, A. Takagi, T. Kamiya, H. Ohta, M. Hirano, and H. Hosono, “Amorphous Oxide Semiconductors for High-Performance Flexible Thin-Film Transistors,” Japanese Journal of Applied Physics, vol. 45, pp. 4303-4308, 2006.
[1.14] H. Q. Chiang, B. R. McFarlance, et al., “Processing effects on the stability of amorphous indium gallium zinc oxide thin-film transistors,” Journal of Non-Crystalline Solids, 2008.
[1.15] K. W. Lee, K. Y. Heo, and H. J. Kim, “ Photosensitivity of solution-based indium gallium zinc oxide single-walledcarbon nanotubes blend thin film transistors,” Applied Physics Letters, vol. 94, 102112, 2009.
[1.16] D. Kahng and S. M. Sze, “A floating gate and its application to memory devices”, Bell Syst. Tech, J., Vol. 46, pp. 1288 , 1967.
[1.17] J. D. Blauwe, “Nanocrystal nonvolatile memory devices”, IEEE Transaction on Nanotechnology, vol. 1, pp. 72, 2002.
[1.18] M. H. White, Y. Yang, A. Purwar, and M. L. French, ”A low voltage SONOS nonvolatile semiconductor memory technology”, IEEE Int’l Nonvolatile Memory Technology Conference, pp.52, 1996.
[1.19] M. H. White, D. A. Adams, and J. Bu, “On the go with SONOS”, IEEE circuits & devices, vol. 16, pp. 22, 2000.
[1.20] J. S. Witters, G. Groeseneken and H. E. Maes, “Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuits”, IEEE Jounal of Solid State Circuits, pp. 1372, 1989.
[1.21] S. Tiwari, F. Rana, K. Chan, H. Hanafi, C. Wei, and D. Buchanan, “Volatile and non-volatile memories in silicon with nano-crystal storage”, IEEE Int. Electron Devices Meeting Tech. Dig., pp. 521, 1995.
[1.22] J. J. Welser, S. Tiwari, S. Rishton, K. Y. Lee, and Y. Lee, “Room temperature operation of a quantum-dot flash memory”, IEEE Electron Device Lett., Vol. 18, pp. 278, 1997.
[1.23] Y. C. King, T. J. King, and C. Hu, “MOS memory using germanium nanocrystals formed by thermal oxidation of Si1-xGex”, IEEE Int. Electron Devices Meeting Tech. Dig., pp. 115, 1998.

Chapter 2
[2.1] H. Yabuta, M. Sano, K. Abe, T. Aiba, et al., “High-mobility thin-film transistor with amorphous InGaZnO4 channel fabricated by room temperature rf-magnetron sputtering”, Applied Physics Letters, vol. 89, 112123, 2006.
[2.2] J. H. Na, M. Kitamura, and Y. Arakawa, “High field-effect mobility amorphous InGaZnO transistors with aluminum electrodes”, Applied Physics Letters, vol. 93, pp. 063501, 2008.
[2.3] J. S. Park, J. K. Jeong, Y. G. Mo, and H. D. Kim, “Improvements in the device characteristics of amorphous indium gallium zinc oxide thin-film transistors by Ar plasma treatment”, Applied Physics Letters, vol. 90, pp. 262106, 2007.
[2.4] T. Y. Chan, K. K. Young, C. Hu, “A true single transistor oxide-nitride-oxide EEPROM”, IEEE Electron Device Lett., Vol. 3, pp. 93-95, 1987.
[2.5] P. Pavan, R. Bez, P. Olivo, and E. Zanoni, “Flash memory cells-an overview”, Proceedings of The IEEE, vol. 85, pp. 1248, 1997.
[2.6] M. Woods, “Nonvolatile Semiconductor Memories：Technologies, Design, and Application”, C. Hu, Ed. New York：IEEE Press, ch. 3, p.59, 1991.
[2.7] Stanley Wolf, “Silicon Processing for The VLSI ERA”, Vol.3, pp.435.
[2.8] M. Lenzlinger, “Fowler-Mordheim Tunneling in thermal grown SiO2”, Applied Physics Letters, vol. 40, pp. 278-283, 1969.
[2.9] P. E. Cottrell, R. R. Troutman, and T. H. Ning, “Hot-electron emission in n-channel IGFETs,” IEEE J. Solid-State Circuits, Vol. 14, pp. 442, 1979.
[2.10] I. C. Chen, C. Kaya and J. Paterson, “Band-to-band tunneling induced substrate hot-electron (BBISHE) injection: A new programming mechanism for nonvolatile memory devices,” IEEE Int. Electron Devices Meeting Tech. Dig., pp.263, 1989.
[2.11] I. C. Chen, D. J. Coleman, and C. W. Teng, “Gate current injection initiated by electron band-to-band tunneling in MOS devices,” IEEE Electron Device Lett., vol. 10, no. 7, pp. 297, 1989.
[2.12] T. Ohnakado, K. Mitsunaga, M. Nunoshita, H. Onoda, K. Sakakiibara, N. Tsuji, N. Ajika, M. Hiyoshi, “Novel Electron Injection Method Using Band- to-Band Tunneling Induced Hot Electron(BBHE) for Flash Memory with a P-channel Cell,” IEEE Int. Electron Devices Meeting Tech. Dig., pp. 279, 1995.
[2.13] San, K. T. Kaya, C. Ma, T. P. “Effects of erase source bias on flash EPROM device reliability” IEEE Transactions of Electron Devices, vol. 42, pp. 150-159, 1995.
[2.14] Steve S. Chung, Cherng-Ming Yih, Shui-Ming Cheng, and Mong-Song Liang, “A new technique for hot carrier reliability evaluations of flash memory cell after long-term program/erase cycles”, IEEE Transactions of Electron Devices, vol. 46, 1999.
[2.15] P. Cappelletti, R. Bez, D. Cantarelli, and L. Fratin, “Failure mechanisms of Flash cell in program/erase cycling”, IEEE Int. Electron Devices Meeting Tech. Dig., pp. 291–294, 1994.
[2.16] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, “Introduction to Flash Memory”, Proceedings of The IEEE, Vol. 91, pp. 489-502, 2003.