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研究生： 王馨珮
Wang, Hsin-Pei
論文名稱： 針對以憶阻器為基礎之邏輯電路來達成運算脈衝數量優化的合成研究
On Synthesizing Memristor-Based Logic Circuits with Minimal Operational Pulses
指導教授： 王俊堯
Wang, Chun-Yao
口試委員: 林榮彬
Lin, Rung-Bin
黃世旭
Huang, Shih-Hsu
學位類別： 碩士
Master
系所名稱：
論文出版年： 2017
畢業學年度： 105
語文別： 英文
論文頁數： 29
中文關鍵詞： 憶阻器 、邏輯合成 、蘊含邏輯 、最小化 、扇出
外文關鍵詞： Memristor, Logic Synthesis, Implication Logic, Minimization, Fanout
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    • 憶阻器(Memristor)這幾年來廣泛應用於各種領域的兩端點奈米元件，例如：機器學習和神經形態系統，引起很大的關注。憶阻器亦可被用於實現蘊含邏輯閘，以及邏輯電路。然而，在以憶阻器為基礎之邏輯電路上，其扇出點有一些限制而需要特別的處理。而在另一方面，除了憶阻器的數量之外，另一種用來測量以憶阻器為基礎之邏輯電路的品質的指標是運算脈衝數量。因此，在本研究中，我們提出以最小運算脈衝數量為目標的合成演算法，來處理使用蘊含閘所構成之以憶阻器為基礎的邏輯電路的扇出問題。我們在MCNC的電路上進行實驗，其結果顯示我們所提出的演算法與現有技術相比，平均可以減少29%的運算脈衝數量和36%的憶阻器總數。

    Memristor, which is a two-terminal nanodevice widely used in various fields, e.g., machine learning and neuromorphic systems, has attracted much attention these years. Memristor can also be used to realize an implication logic gate and thus logic circuits. However, the fanouts in a memristor-based logic circuit have some constraints and need to be processed with special care. On the other hand, in addition to the number of memristors, the number of operational pulses is another metric to measure the quality of a memristor-based logic circuit. Hence, in this thesis, we propose a synthesis algorithm to deal with the fanout problems in memristor-based logic circuits using implication logic gates for having a minimal number of operational pulses. We conducted experiments on a set of MCNC benchmarks. The experimental results show that the proposed algorithm can reduce 29% operational pulses and 36% memristor count on average compared with the state-of-the-art.

    1 Introduction 1 2 Preliminaries 5 2.1 Implication Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 Constructing NOT and NAND Using IMPLY Gates . . . . . . . . . . 7 2.3 Fanout Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Algorithm 9 3.1 Fanout Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.2 Proposed Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 Overall Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4 Experimental Results 22 5 Conclusion 26

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