隨著電子產品輕薄短小及功能多樣化之潮流，由傳統之二維封裝型態轉移至新型之三為堆疊封裝已為必然之趨勢。對三維堆疊封裝而言，晶圓級封裝(Wafer Level Package, WLP)技術可以覆晶(Flip Chip, FC)之方式直接於晶圓上完成封裝之製程並擁有良好之重工性，因而可有效降低三維堆疊封裝或系統式封裝(System in Package, SiP)之製程成本。
本論文中亦提出一具有堆疊及扇出(Fan-out)特性之新式具金屬載板之嵌板型晶圓級封裝(Chip-on-Metal Panel Level Package, COM PLP)，其先將晶片黏著於金屬晶片載板上，再利用高分子聚合材料填充晶片周圍之孔穴，透過圍繞於晶片四周之高分子聚合物材料可使晶片之電訊接點重新分佈並增加其接點間距，達到扇出之目的。另一方面，本封裝結構中之軟性高分子材料可作為應力緩衝層，進一步增加結構中焊錫接點之使用壽命。此外，本結構使用具有導電特性之金屬晶片載板，將可同時有效釋放內埋晶片於使用中所產生之熱能。
為清楚瞭解所提出之新式嵌板型晶圓級封裝之熱-機械力學特性與散熱效能，本論文針對所提出之封裝結構建立上板後之有限元素模型進行參數化分析。根據參數化分析之結果，更進一步參考統計實驗設計中因子設計法(Factorial Designs)進行敏感度分析(Analysis of Variance, ANOVA)，藉此獲得各設計因子之敏感度與因子間交互作用之關係。
研究結果指出此新式封裝結構中焊錫接點之疲勞壽命有相當優異之表現，因此破壞模式轉換為須同時考量電訊接點以及結構內部貫通電極或金屬線路之偶合形式。於熱傳分析方面，本新式封裝結構因使用金屬晶片載板而保持類似覆晶封裝之良好散熱能力。最後根據本論文中對於結構可靠度以及散熱效能之研究，可依照不同之設計參數歸納出對應之設計規範，其望可作為後續研究之參考。

With the current trend in multi-functioning and minimizing the volume of electronic products, it is now necessary to shift from traditional two-dimensional packaging into three-dimensional (3-D) stacked packaging. In 3-D stacked packaging, the wafer-level-package (WLP) may be an effective solution because it completes the packaging operation directly on the wafer in flip chip manner and has good re-workability, which could reduce packaging costs in stacked packages and multi-chip modules.
In this paper, a new packaging technology, chip-on-metal (COM) panel level package (PLP) with stacking and fan-out capabilities, is proposed. The concept of this package is to use the filler polymer material to pack the trench of the chip which is back-sided attached to the metallic chip carrier. Therefore, the solder bumps could be located on both the filler polymer and the chip surfaces by the redistribution lines and the pitch of the chip side is fanned-out. In addition, the soft polymer material could be treated as the stress buffer layer to improve the solder joint fatigue life. Moreover, the metallic chip carrier could be helpful in dissipating the generated heat from the chip.
To assess the thermo-mechanical characteristic and thermal performance of the proposed PLP, the finite element analysis (FEA) in the board level is carried out. The parametric analysis of the COM PLP is studied to enhance its reliability characteristic and thermal performance. Furthermore, the factorial designs with the analysis of variance (ANOVA) are conducted to obtain the sensitivity information and interaction relationship between factors of the COM PLP.
The results of this study showed that the predicted life cycles of solder joints in the PLP is found to possess outstanding performance. However, the stress concentration in via-through-holes (VTH) and redistribution traces may become another failure mechanism. In terms of thermal performance, the metallic chip carrier can rapidly dissipate the heat generated from the chip. Based on the reliability and thermal performance assessment, the design windows of the COM PLP and stacked PLP are established. Finally, this study is expected to become an important reference material for future research.

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