本論文提出一個以標準元件庫細胞為基礎的時間量化器電路架構及其電路自動產生軟體來自動產生符合需求的時間量化器電路。由於製程檔所提供的數據為近似值，再加上結果會隨著自動佈局階段擺放位置與繞線不同而產生變異，使得脈衝萎縮模組的量化結果與預期不太相符。為了解決這個問題，微調元件的解析度都會預先做電晶體層的模擬驗證，由此可整理出在台積電90nm製程下適合縮減脈衝寬度架構之微調元件。額外加上一個可調控萎縮量的粗調電路能使整個架構更穩定不受製程變異影響。最後解碼器的輸出結果會由內差法轉變到時域上的值讓後端使用更直觀方便。內差過程中會利用多次取樣的方法來降低時脈訊號抖動所造成的誤差。我們提出的系統能在數分鐘內產生出符合使用者需求的時間量化器，並節省設計流程所要消耗的資源與時間成本。該時間量化器電路編譯軟體能支援1ns至8ns的輸入範圍，並有數種微調元件可供選擇，大幅增加使用的彈性。

This thesis proposes a cell-based Time-to-Digital Converter (TDC) architecture and its compiler, which can generate cell-based TDC circuits automatically. Because the values from data book are approximations and the result could vary from different routing conditions in APR stage, the quantized outcome of shrinking line may not meet the expectations. In order to solve this problem, the resolution of fine-shrinking cells are pre-confirmed in transistor level simulation. It also reorganizes the components that are suitable for pulse-shrinking architecture in TSMC 90nm CMOS process technology. A coarse block with an adjustable shrinking amount is used to prevent the side effects of the process variation. The output digital code is turned into an absolute value by a built-in interpolation scheme to make the back-end operation intuitively. The error caused by clock jitter during the interpolation is reduced by a multi-sample methodology. The proposed system can generate a TDC circuit in minutes with user’s specification. It saves not only time but effort in the design flow. The result from simulation shows that the proposed TDC compiler can support input range from 1ns to 8ns with many choosable shrinking cells and different target ranges. These features increase the flexibility of TDC compiler greatly.

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