這篇論文裡提出了在靜態隨機存取記憶體(Static Random Access Memories, SRAM)中一個全新的時序控制方法，來增強因為製程漂移造成在位元線 (bitline)上變動的容許能力，而位元線上的變動可能會造成感測放大器對位元線上資料的判讀錯誤，所以位元線上的變動容許能力相對地就變得相當重要；而這個方法便是修改了在感測放大器的周邊電路，讓SRAM每一行在操作的時侯，都可以偵測每一行位元線上的變化，，當位元線上的電壓變化到達我們要求的電壓範圍值時，便立即致能感測放大器，而這樣的方式可以使閂鎖型的感測放大器致能在正確的時間。並且也可以最佳地決定字元線(wordline)開啟的脈波寬度，以減少功率的消耗。
在以pre-layout的方式模擬方面，我們針對良率的觀點來看，本篇論文提出來的方法和目前被廣泛使用以Replica column為基礎的靜態隨機存取記憶體來做比較，在製程漂移為□10%條件下，並變動感測放大器的臨界電壓來造成不匹配的情形，以蒙地卡羅方式取樣1000次，本篇論文提出來的方法良率可達96.3%，而以Replica column為基礎的靜態隨機存取記憶體良率卻只有79.2%。由此可見每行獨立時序控制之架構確實有抵抗製程漂移的免疫能力。
我們以實際的post-layout方式模擬1K-bit的靜態隨機存取記憶體來佐證本篇論文提出來的方法，而這個方法確實可以增強製程漂移和雜訊的免疫能力。

This thesis presents a new timing-tracking scheme in an SRAM design for enhancing the tolerance capability of bitline variation. This scheme, modifying the circuitry around each sense amplifier, allows an SRAM column to operate according its own timing. Thus, each latch-based sense amplifier can be turned on at the right time and the pulse width of the active wordline can be tuned to its optimal width on the fly, no matter how severe the operation speed of a bitline differs from the other.
Pre-layout SPICE simulation with 1K-bit SRAM cells demonstrates the effectiveness of this scheme. Monte-Carlo simulation with 10% process variation shows that our scheme can improve the yield from 79.2% to 96.3%, as compared to the traditional replica-based timing tracking scheme.

[1] K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda, “A Bitline Leakage Compensation Scheme for Low-Voltage SRAMs,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 5, pp. 726-734, May 2001.
[2] B. S. Amrutur and M. A. Horowitz, "A Replica Technique for Wordline and Sense Control in Low-Power SRAM’s", IEEE Journal of Solid-State Circuits, Vol. 33, No. 8, pp. 1208-1219, August 1998.
[3] M. Badaroglu et al., “Methodology and Experimental Verification for Substrate Noise Reduction in CMOS Mixed-Signal ICs with Synchronous Digital Circuits,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 11, pp. 1383-1395, Nov. 2002.
[4] M. J. Chang et. "Supply and Substrate Noise Tolerance Using Dynamic Tracking Clusters in Configurable Memory Designs," IEEE Proc. International Symposium Quality Electronic Design, pp.297-302, 2004.
[5] Y.-C. Lai and S.-Y. Huang, “X-Calibration: A Wide-Range Leakage Current Cancellation Technique for Nanometer SRAM Deigns”, Proc. of Int’l SoC Design Conf., Oct. 2006.
[6] M. Nagata, J. Nagai, K. Hijikata, T. Morie, and A. Iwata, “Physical Design Guides for Substrate Noise Reduction in CMOS Digital Circuits,” IEEE Journal of Solid-State Circuits, Vol. 36, No. 3, pp. 539-549, Mar. 2001.
[7] U. Schlichtmann, “Tomorrow’s High-Quality SoCs Requires High-Quality Embedded Memories Today,” IEEE Proc. Int’l Symposium on Quality Electronic Design, p.225, Mar. 2002.
[8] Y. Ye, M. Khellah, D. Somasekhar, A. Farhang, and V. De, “A 6-GHz 16-kB L1 Cache in a 100-nm Dual-VT Technology Using a Bitline Leakage Reduction (BLR) Technique,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 5, pp. 839-842, May 2003.
[9] T. Kobayashi, K. Nogami, T. Shirotori, Y. Fujimoto, O. Watanabe, "A Current-mode Latch Sense Amplifier and A Static Power Saving Input Buffer for Low-power Architecture", IEEE VLSI Circuit, No. 8, pp. 28-29, June 1992.
[10] Neil H.E. Weste, D. Harris, “CMOS VLSI Design A Circuits and Systems Perspective” Addison Wesley, 2005.
[11] 蕭培墉, 吳孟賢, “HSpice 積體電路設計分析與模擬導論,” 東華書局, July 2005.
[12] B. Amelifard, F. Fallah, M. Pedram, “Low-leakage SRAM Design with Dual Vt Transistors,” IEEE Proc. International Symposium Quality Electronic Design, pp.27-29, March 2006.
[13] S.K. Jain, P. Agarwal, “A Low Leakage and SNM Free SRAM Cell Design in Deep sub Micron CMOS Technology,” IEEE International Conference VLSI Design , pp.3-7, December 2006
[14] C.H. Kim, J.J. Kim, I. J. Chang and K. Roy, “PVT-Aware Leakage Reduction for On-Die Caches with Improved Read Stability,” IEEE Journal of Solid-State Circuits, Vol. 41, No. 1, pp. 170-178, Jan. 2006.
[15] H.Y. Huang, J.F. Lin, “Design and Application of CMOS Bulk Input Scheme,” IEEE Journal of Solid-State Circuits, Vol. 39, No. 8, pp. 1305-1312, Aug. 2004.
[16] T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, “A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture,” IEEE Journal of Solid-State Circuits, Vol. 28, No. 4, pp. 523-527, April 1993.
[17] K. Zhang, U. Bhattacharya, Z. Chen, F. Hamzaoglu, D. Murray, N. Vallepalli, Y. Wang, B. Zheng, and M. Bohr, “ A 3-GHz 70-Mb SRAM in 65-nm CMOS Technology With Integrated Column-Based Dynamic Power Supply,” IEEE Journal of Solid-State Circuits, Vol.41, No. 1, pp. 146-151, Jan. 2006.