多級電路的電容共用偏移電壓補償法｜國立清華大學博碩士論文庫

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研究生：	張椿宏 Chun-Hung Chang
論文名稱：	多級電路的電容共用偏移電壓補償法 A Capacitor Sharing Method for Multi-Stage Offset Compensation
指導教授：	連振炘 Chen-Hsin Lien
口試委員:
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2001
畢業學年度：	89
語文別：	中文
論文頁數：	91
中文關鍵詞：	自動歸零、比較器、遲滯限壓器、濾波器、偏移電壓
外文關鍵詞：	auto-zero, comparator, hysteresis limiter, filter, offset voltage
相關次數：	點閱：1 下載：0
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論文中提出了一種多級電路的電容共用偏移電壓補償法。第一級利用時序1和時序2時的電壓差來消除偏移電壓，第二級則利用閉迴路的自動歸零(輸入儲存)技術來消除偏移電壓。對一個單端輸出的兩級電路而言, 原本需要使用兩個電容來作偏移電壓補償, 現在只需使用一個電容即可達成, 能大幅降低佔面積的電容之使用。
此種方法能廣泛應用於多級電路上, 例如：比較器系統或頻率鍵移(FSK)訊號處理系統等。我們即分別設計三種包含切換式電容預先放大器的比較器, 或者包含切換式電阻預先放大器的比較器，其中串聯的二級預先放大器即採用此法來作偏移電壓之補償。我們將這些比較器設計成乒乓架構，使電路能操作的時間，進一步提升到接近能連續地處理訊號。我們也設計了頻率鍵移(FSK)訊號處理系統中, 濾波器和遲滯限壓器部份的電路。串聯的濾波器和遲滯限壓器也採用此法來作偏移電壓之補償。我們以混合訊號模式來設計此電路，並且使用CADANCE積體電路輔助設計工具及運用Full-Customer 設計方式來實現混合積體電路架構。

HSPICE模擬結果可將偏移電壓降至低於0.3%, 而利用TSMC 0.35mm CMOS製程所作出的晶片量測結果也顯示, 偏移電壓可以小至微米級。配合理論推導及模擬結果作分析，可證明電容共用偏移電壓補償法可應用於多級電路之設計上。

We propose a capacitor sharing method for multi-stage offset compensation. The offset voltage of the 1st stage can be compensated using the difference of voltages at output between two phases. The offset voltage of the 2nd stage can be canceled using a closed loop auto-zero compensation technique ( input storage ). Only one capacitor is required for a multi-stage circuit in case of single-ended implementation.
The method can be applied to many types of a multi-stage circuit. Such as comparators, frequency shift keying (FSK) signal process system and so on. In the application of comparators, for example, only one capacitor is needed between two pre-amplifiers that are serial connection to compensate offset voltages. We proposed three comparator circuits with switched-capacitor amplifiers or switched-resistor amplifiers based on ping-pong structure. They can increase the active time. Similarly in the FSK signal process system, only one capacitor is needed between the high-pass filter and hysteresis limiter that are serial connection to compensate offset voltages. Such a circuit is mixed-signal mode, and thus we need to use the CADANCE tools to design the circuit.

The HSPICE simulation of the designed compensation circuit shows that the input offset voltage can be reduced to less than 0.3%. It is realized by using TSMC 0.35mm CMOS process. The measurement result shows that we can reduce the offset voltage to mv level. The results prove that the capacitor sharing method is useful for multi-stage offset compensation.

Abstract
Contents

Chapter 1: Introduction................................................................................................................1

Chapter 2 : Principle of offset voltage compensation...................................................................4

2-1 Introduction of offset voltage................................................................................................4

2-1-1 Causation of offset voltage.................................................................................................4

2-1-2 Calculation of offset voltage...............................................................................................4

2-1-3 Influence and importance...................................................................................................7

2-1-4 Trend of offset voltage........................................................................................................8

2-2 Introduction of compensation method....................................................................................8

2-2-1 Classification and comparison.............................................................................................9

2-2-2 Auto-zeroing (output storage & input storage...................................................................10

2-2-3 Chopper stabilization........................................................................................................13

2-2-4 Floating gate MOS............................................................................................................14

Chapter 3 : Circuit Architecture and Simulation.........................................................................15

3-1 Principle of capacitor sharing method..................................................................................15

3-2 Design of components.........................................................................................................16

3-2-1 Design consider of MOS switch.......................................................................................16

3-2-2 Design of amplifier or filter..............................................................................................17

3-2-3 Design of comparator.......................................................................................................17

3-2-4 Design of multi-stage.......................................................................................................18

3-2-5 Design of ping-pong structure..........................................................................................18

3-3 Application circuit...............................................................................................................19

3-3-1 Comparator circuit with general SC-Amp.........................................................................19

3-3-2 Comparator circuit with SR-Amp......................................................................................21

3-3-3 Comparator circuit with reformed SC-Amp.......................................................................23

3-3-4 Filter and hysteresis limiter circuit.....................................................................................26

3-4 OP Amp and chip specification............................................................................................31

Chapter 4 : Layout Description...................................................................................................32

4-1 Layout consideration............................................................................................................32

4-2 Layout of complete circuits..................................................................................................37

Chapter 5 : The Measurement Result and Discussions................................................................39

5-1 The methods and measurement............................................................................................39

5-2 High-pass SC filter...............................................................................................................40

5-3 Offset voltage compensation................................................................................................40

5-3-1 Common mode voltage input............................................................................................40

5-3-2 Common mode voltage input with assigned offset voltage................................................41

5-3-3 Periodic square wave input................................................................................................42

5-3-4 Random square wave input................................................................................................42

Reference....................................................................................................................................43

Figure..........................................................................................................................................45

Figure of Chapter2.......................................................................................................................45

Figure of Chapter3.......................................................................................................................50

Figure of Chapter4.......................................................................................................................73

Figure of Chapter5.......................................................................................................................81

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