本論文針對先進製程佈局設計，在兩個不同層面下逐一對四個問題進行探討。首先，第一個層面著重於工程變更指令(engineering change order，簡稱為ECO)，主要專注於具冗餘接點(redundant via)意識的ECO繞線與具光罩(mask)成本意識的ECO繞線；而第二個層面著重於三重圖案微影技術(triple patterning lithography, 簡稱為TPL)，主要針對以標準元件為基礎(cell-based)的列狀佈局(row-structure layout)研究其TPL分解，進而再探討具TPL意識的細部擺置改進(detailed placement refinement)。

當完成晶片的擺放與繞線後(place-and-route)或甚至是下線(tape-out)之後，為了快速修正功能與時序問題，工程師可以利用預先嵌入的備份元件(spare cell)來改變原始的電路，並針對變更的連線(net)透過ECO繞線來連接。然而在奈米尺度下為了提升晶片良率和可靠度，冗餘接點安插已成為必然的手段;但當ECO繞線將現有佈局物件(layout object)視為障礙物時，安插了冗餘接點會造成剩餘的繞線資源變得相當有限，進而使ECO繞線更加難以實現。因此我們提出了能針對冗餘接點做置換、移除及安插的ECO繞線方法。另外我們也特別針對後矽(post-silicon)階段的ECO實作，研究了另一個ECO繞線問題;此問題考慮了四種修改電路的手段，其中包含了新增連線(net addition)、刪除連線(net deletion)、腳位連接(pin connection)及腳位斷開(pin disconnection)。因為隨著製程技術不斷的進步，光罩成本變成是一個在後矽階段關鍵的議題，所以在此ECO繞線問題之下，我們提出了能考慮重新利用以前的繞線(old route)來節省光罩成本的ECO繞線方法。

在過去幾年內針對先進的微影技術TPL，佈局設計技術備受關注，已有數個TPL相關的問題被探討，其中包含了佈局分解以及具TPL意識的元件擺置。首先，TPL佈局分解問題是將同一層(layer)內的多邊形圖案(polygon)分配到三個不同的光罩，若被分配到同一個光罩的兩個圖案，彼此間的距離不能低於TPL所規範的最小著色間距(minimum coloring distance)，否則會形成一個著色衝突。針對以標準元件為基礎且位於第一層金屬層(Metal 1 layer)上的列狀佈局，我們設計了以圖論為基礎的方法來解決TPL佈局分解問題，此方法會求得一個分解結果並最小化關於著色衝突及縫合圖案(stitch)的總成本。另外我們也開發數個圖形簡化的技巧來加速我們的分解方法。最後，為了進一步提升TPL佈局分解品質，我們在細部擺置階段探討TPL，並提出了以元件列為基礎(row-based)的細部擺置改進方法，求得無著色衝突的合法擺置(legal placement)且最小化其縫合圖案數量與線長(wirelength)。

This dissertation studies four problems of advanced layout design in two different aspects. For engineering change order (ECO), we focus on redundant-via-aware ECO routing and mask-cost-aware ECO routing; for triple patterning lithography (TPL), we first investigate cell-based row-structure TPL layout decomposition and then TPL-aware detailed placement refinement.

For the purpose of fixing functional and/or timing problems effectively and efficiently after place-and-route or even tape-out, designers can utilize pre-injected spare cells to change the original design and apply ECO routing to connect modified nets incrementally. However, redundant via insertion (RVI) has become an inevitable means adopted in the routing or post-routing stage to enhance chip reliability and yield as feature size shrinks down to nanometer scale. The remaining routing resources could become so limited after RVI, thus causing difficulties in ECO routing which regards existing layout objects as routing blockages. We propose an ECO routing approach that considers redundant via replacement, removal, and insertion. We also address another ECO routing problem, especially for post-silicon ECO implementation; this problem considers four types of circuit modifications: net addition, net deletion, pin connection, and pin disconnection. As minimum feature size continues to scale down, the cost of photomasks becomes a critical issue for post-silicon ECO. We present an ECO routing approach that considers the reuse of old routes to save the mask re-spin cost.

In the past few years, much attention has been devoted to layout design with the advanced lithography technology, TPL.
Several relevant problems in TPL, such as layout decomposition and TPL-aware placement have been explored.
The TPL layout decomposition problem is to divide the polygons on a layer into three different masks, in which the distance between two polygons assigned on the same mask should not be less than the minimum coloring distance in TPL, or a coloring conflict is caused. For any cell-based row-structure layout on Metal 1 (M1) layer, we design a graph-based approach to solve the TPL layout decomposition problem by finding a decomposition solution with the minimal total cost in terms of conflicts and stitches. We also develop several graph simplification methods to speed up our approach. To enhance the decomposition quality, we finally study TPL in the detailed placement stage. We present a row-based detailed placement refinement approach which aims at finding a legal placement with a conflict-free TPL layout decomposition and meanwhile minimizing the number of stitches and the wirelength.

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