近年來，矽-二氧化矽-氮化矽-二氧化矽-矽（SONOS）型記憶體逐漸成為非揮發性記憶體發展之重點，然而隨著製程之演進，SONOS型記憶體亦面臨到尺度微縮之問題，因此本篇論文主要針對氮化矽層本身厚度之縮減來探討SONOS型記憶體電特性變化以及可靠度之問題。
實驗中利用通道熱電子注入（CHEI）機制、帶對帶穿隧熱電洞注入（BBHHI）機制與福勒-諾德漢穿隧（Fowler-Norheim Tunneling）機制來進行寫入與抹除之動作，實驗結果發現，由於沉積之穿隧氧化層厚度偏厚，以致於利用福勒-諾德漢穿隧機制進行抹除反而使臨界電壓有上升趨勢，因而無法進行抹除動作。除此之外，隨著氮化矽層厚度之縮減，造成臨界電壓有變小之趨勢，對於記憶體之寫入與抹除速度皆能有效提升。
在可靠度探討方面以耐久度（Endurance）與保持度（Retention）為主要探討議題，實驗結果也發現，較薄之氮化矽層厚度在重複寫入抹除循環後，其寫入與抹除臨界電壓值隨著循環次數增加而急速上升，造成記憶體窗（Memory Window）大幅微縮而降低元件之耐久度。雖然可以利用加強抹除時間與增加抹除之汲極端偏壓來抑制記憶體窗微縮之情況，卻會造成速度衰退以及額外的功率消耗。此外，記憶體於寫入狀態時，經由長時間高溫烘烤下，氮化矽層內部儲存電荷因為厚度縮減而有明顯漏電之趨勢，造成臨界電壓大幅下降，進而加速元件保持度之衰退。

Recently, Flash technology is gradually migrated from floating-gate cells to charge-trapping devices due to lower operating voltage and two bits storage. However, it is also a great challenge to scale the conventional charge-trapping Flash cells for the need of high voltage operations in channel-hot-electron (CHE) programming and band-to-band-hot-hole (BBHH) erasing.
This thesis experimentally examines the scaling effects of the nitride charge-trapping layers on Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type Flash memory. The reduction of nitride charge trapping layer offers the enhancement of programming and erasing speed for the SONOS type memory cell. However, it leads to the serious degradations in the memory window during 10K programming/erasing cycling and the retention charge loss after 10K cycling stress. Trade-offs between the performance enhancement and cell reliability exist to limit the further scaling of charge trapping layers for future non-volatile memory cells.

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