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研究生: 陳聖文
Chen, Sheng-Wen
論文名稱: 應用於光連結系統之高速前端電路與光電介面交換機設計
High-speed Optical Front-end Circuits and STDM Switch with Optical Interconnect Interface
指導教授: 徐碩鴻
Hsu, Shuo-Hung
口試委員: 邱煥凱
Chiou, Hwann-Kaeo
朱大舜
Chu, Ta-Shun
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電子工程研究所
Institute of Electronics Engineering
論文出版年: 2013
畢業學年度: 101
語文別: 英文
論文頁數: 62
中文關鍵詞: 限制放大器轉阻放大器雷射驅動電路STDM交換機光連結系統主動電感ESD電路CML電路圖騰柱輸出級
外文關鍵詞: Limiting amplifier, Transimpedance amplifier, Laser diode driver, STDM switch, Optical interconnect system, Active inductor, ESD circuit, CML circuit, Totem pole output stage
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  • 隨著資料傳輸與處理速度加快,為了解決傳統金屬走線非理想效應,光通傳輸介面被應用於晶片間或晶片內傳輸,稱為光連結系統。本論文分為五章,前四章分別對光連結系統收發機前端電路進行介紹與設計,並在第五章把前端電路與高速交換機做結合,達到真正整合光電傳輸介面之高速交換機。


    With the increasing speed of data transmission and processing, in order to solve the non-ideal effects of conventional electrical interconnect, O/E interface is proposed to be used in chip-to-chip or intra-chip level transmission, known as the optical interconnect (OI). This thesis including five chapters focuses on designing the high-speed optical front-end blocks for OI applications. The first four chapters describe optical transceiver front-end circuits, and the optical front-end blocks are combined with a 4×4 high-speed switch to achieve a fully-integrated high-speed switch with OI interface in chapter 5.

    致謝 ii ABSTRACT iii 摘要 v CONTENTS vii LIST OF FIGURES ix Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Design Considerations 3 Chapter 2 10 GB/s Indoctorless Limiting Amplifier 4 2.1 General Structure of LA 4 2.2 Proposed LA in 0.18μm CMOS Technology 5 2.2.1 Order of Gain Cell 5 2.2.2 Gain Cell 6 2.2.3 DC Offset Voltage Cancellation Loop 8 2.2.4 Output Buffer 10 2.3 Simulations and Measurement Results 11 Chapter 3 40Gb/s Transimpedance Amplifier 15 3.1 The Principles of TIA Design 15 3.2 Proposed High Speed & Low Power TIA 17 3.2.1 Inverter-type Input Current Buffer 17 3.2.2 Transformer Peaking Technique 19 3.2.3 Second Stage and Output Buffer 22 3.3 Simulations and Measurement Results 24 Chapter 4 10 Gb/s Laser Diode Driver 29 4.1 Design Considerations for LDD 29 4.2 Proposed inductorless LDD 31 4.2.1 Totem-pole Output Stage 31 4.2.2 Pre-driver Design 34 4.3 Simulations and Measurement Results 36 Chapter 5 80 Gb/s STDM O/E Interface Switch 39 5.1 Introduction of STDM Switch 39 5.2 O/E Interface Switch in 40nm CMOS Technology 41 5.2.1 High-speed STDM Switch Block 42 5.2.2 Receiver Front-end 45 5.2.3 Transmitter Front-end 48 5.2.4 ESD Protection 49 5.3 Simulation Results 50 5.4 Measurement Consideration 55 5.4.1 Switch Function Measurement 55 5.4.2 High-Speed On-Wafer Measurement 56 5.4.3 Bit-Error-Rate-Testing 57 5.4.4 High-Speed O/E Measurement 57 References 59

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