研究生: |
鐘元彬 Yuan-Bin Chung |
---|---|
論文名稱: |
應用金屬閘極與阻擋層整合矽鍺通道以改善電荷陷阱式快閃記憶體元件之效能 Operation of enhancement on charge trapping flash memory devices with integration metal gate and blocking layer and Si-Ge channel |
指導教授: |
張廖貴術
Kuei-Shu Chang-Liao |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
原子科學院 - 工程與系統科學系 Department of Engineering and System Science |
論文出版年: | 2008 |
畢業學年度: | 96 |
語文別: | 中文 |
論文頁數: | 124 |
中文關鍵詞: | 電荷陷阱式快閃記憶體 |
相關次數: | 點閱:3 下載:0 |
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浮動閘極結構的穿隧氧化層厚度約8nm,而SONOS結構的穿隧氧化層大都在3nms左右,所以如何在不變動穿隧氧化層的前提下,仍使元件保証有十年以上的電荷保存力(Data Retention)且能加快元件操作,如抹除操作,是SONOS結構面臨的最主要課題之一
本論文的研究重點主要包含兩個方向:
(1) 利用高功函數金屬會使能帶彎曲的特性,加快元件操作包括寫入與抹除,雖然這有犧牲一點資料保存能力,但整體起來是值得的。氮化鉬(MoN)金屬閘極是最好的証據,他擁有最佳的寫入與抹除操作,但資料保存能力相對較差。後續實驗則是如何保持住金屬高功函數的優點,使其不在後續製程,或與阻擋層整合時發生不良效果。我們使用堆疊結構的金屬閘極(TiN100/MoN400),可以改善與二氧化矽的整合問題,但與氧化鋁整合則效果差。
(2) 利用磊晶的矽鍺薄膜當N型通道材料,並取其對於價帶會產生彎曲產生一位能井的特性,有利於電洞穿隧進入儲存層的優點,期望可以加快抹除操作,且不損傷資料保存能力。由實驗中發現當退火溫度高,且鍺含量為11%,覆蓋的矽薄膜厚度為10Å時這矽鍺通道對元件的改善最明顯。
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