本研究探討場發射金屬氧化半導電晶體（MOSFET）淺溝槽隔離絕緣層（Shallow Trench Isolation，STI）與鄰近電晶體主動區的高度差（Step-height）對元件特性的影響。
實驗採用化學機械研磨（Chemical Mechanical Planarization，CMP）及氫氟酸（HF）蝕刻兩種方式來製造高於或低於標準的絕緣層高度差，討論其對元件隔離特性的接面漏電流（Junction Leakage）及元件之特性，包含短通道效應（Short Channel Effect，SCE）、窄通道效應（Narrow Width Effect，NWE）等的影響。
在定性分析方面，發現最後的STI物理立體結構與最初的CMP或HF蝕刻完成時之Step-height有著非常密切的關係，基本上不管以何種方式產生的Step-height都是呈現遞減的線性相關，Divot深度的變化也呈現相同的趨勢，但遞減趨勢較為緩和。
在定量分析部分，我們找出特定元件圖形（Pattern）之厚度與Step-height的關係，其中CMP的Nitride厚度與Step-height的關係為0.43：1；HF蝕刻的Oxide厚度與Step-height的關係為1.77：1。
在電性分析部分，當起始Step-height由660 Å下降到170 Å時，小尺寸（Clearance為 0.08 μm）元件之Inter-well 漏電流分別有3 ~ 5個數量級的差異。在NWE方面，小尺寸（寬度為 0.12 μm）元件之汲極飽和電流（Idsat）有 10 ~ 20 ﹪的強化。在SCE方面，短通道（長度為50 nm）元件之DIBL（Drain Induced Barrier Lowering）特性有9.8 ~ 16.5 mV/V的差異。另外，我們利用三組面積與週長不同大小的Pattern，估算出面積與週長對接面漏電流的個別貢獻，結果顯示面積對與漏電流貢獻約是週長的22 ~ 24倍，藉此關係可估算出已知面積與週長Pattern之漏電流，若Step-height在660 ~ 390 Å範圍內，其誤差可小於 10 ﹪。
本研究將製程之厚度參數與Step-height及元件電性做連結，我們可藉此來監控導致元件特性異常的製程，並可進一步以此為先進製程控制（Advanced Process Control，APC）的發展基礎，對製程良率的提升是一個重要的參考。

This research studies the effect on device performance from the step-height difference between Shallow Trench Isolation (STI) and its neighboring transistor active-region in Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
The study utilizes the two methods of Chemical Mechanical Planarization (CMP) and Hydro-Fluoric Acid (HF) wet etch to create dielectric step-height difference higher or lower than standard, than discuss the effect on transistor isolation properties, specifically Junction Leakage and it’s effect on device performance, including Short Channel Effect (SCE), Narrow Width Effect (NWE), etc.
For qualitative analysis, it was discovered that the final STI physical structure is determined by the initial step-height right after CMP or HF wet-dip process is finished. It is gradually decrease correlations both step-height and divot.
On quantitative analysis, we find out the relationship of specific pattern thickness versus the outcome of step-height. The relationship of CMP Nitride thickness and step-height was found to be 0.43：1; HF wet-dip oxide thickness and step-height’s relationship was found to be 1.77：1.
In electrical performance, the results show that when step-height was reduced from 660 Å to 170Å, 3 to 5 order of magnitude difference in Inter-well leakage was found in the minimum feature transistor (clearance 0.08 □m). For NWE property, there was a 10 to 20% enhanced in saturation drain current (Idsat) for the narrowest width device (0.12 □m). For SCE property, 9.8 to 16.5 mV/V difference on DIBL was found for the shortest tunnel-length device (50 nm). It is shown that transistor performance can be significantly affected by step-height change. Besides, we employed 3 patterns of difference sizes, attempting to find the individual contribution of perimeter and area on interface leakage. The results show that area’s contribution to leakage is 22 to 24 times as much as perimeter’s contribution, indicating the device size as the determining factor for device leakage. We can make use of this relationship to calculate the leakage value for patterns with known area and perimeter; for step-height between 660 to 390 Å, the error margin is within 10%.
This study links the relationship of the process thickness parameter between step-height and electrical performance; the result can help control device abnormality, furthermore can be the development basis for Advanced Process Control, thus be used as an important reference for process control and yield improvement.

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