近年來數位電路發展迅速，拜製程進步之賜，數位電路在速度上與運算處理能力大為提升，並且能夠儲存大量的數位資料，儘管如此，數位電路跟外界溝通與傳遞還是必須透過類比數位轉換器與數位類比轉換器，在高速傳遞要求下，本論文設計出高效能十位元每秒取樣五千萬次脈管式類比數位轉換器且包含數位修正電路搭配分享型共用運算放大器、Switch Boostrapped、增益增強(Gain Boosting)…等等電路設計技巧，來設法讓電路能夠在低功率消耗情況下讓效能提高，以符合電子電路發展趨勢。

類比數位轉換器特性在輸入全擺幅正弦波，頻率為1.28 MHz正弦波模擬結果能得到為雜訊位準-85 dB，全諧波失真-65.5 dB，訊號對雜訊及失真比59.8 dB。在電源電壓為2.5伏特時所消耗的功率為31mW，另外，在輸入全擺幅正弦波，頻率為2 MHz正弦波模擬結果能得到為雜訊位準-60 dB，全諧波失真-25.5 dB，訊號對雜訊及失真比22dB。在電源電壓為3伏特時所消耗的功率約為50mW，晶片面積含I/O Pads約為3.45 mm2，並採用TSMC 0.35µm 2P4M Standard CMOS製程加以實現並封裝。

A 10-bit 50-MS/s pipelined analog-to-digital converter (ADC) using an operational amplifier sharing technique in TSMC 0.35µm standard CMOS process technology is presented. A new method to suppress the effect of kickback noise in the low offset comparator is also presented.

The simulated ADC performances achieve -85 dB of Noise Level ,-65.5 dB of THD、59.8dB of SNDR for 1.28 MHz input signal. Under 2.5-V supply, the power consumption of the proposed ADC is 31-mW. The measured ADC performances achieve -60 dB of Noise Level ,-25.5 dB of THD、22 dB of SNDR for 2 MHz input signal. Under 3-V supply, the power consumption of the proposed ADC is 50-mW. The chip area including I/O pads is 3.45 mm2.

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