在這項研究中，採用CMOS 0.18μm 1P6M技術來製造用於輻射感測器的16通道前端讀取晶片。 此晶片讀取輻射偵測器的電流訊號，並使用非二進位逐次逼近暫存器（SAR）類比數位轉換器（ADC）將此訊號轉換為數位串列數據，取樣率為1 MS/s，解析度為10位元. 此晶片的最小（最大）微分非線性和積分非線性經測量分別為-0.32（0.33）和-0.43（0.37）最低有效位。 在輸入頻率為 500 kHz、取樣率為 1 MS/s 時，訊號雜訊失真比和有效位數分別確定為 57.41 dB 和 9.24 位元。 所開發晶片的 SAR ADC 在取樣率為 1 MS/s 時的品質因數為 38.9-fJ/conversion-step。 所開發的晶片可以讀取峰值電流範圍為20至750μA的輸入訊號，並且可以將類比訊號轉換為10位元串列輸出數位訊號。 此晶片的輸入動態範圍為2-75 pC，電流解析度為208.3 nA，面積為1.444 mm × 10.568 mm，每通道功耗為19 mW。 為了提高 SAR ADC 性能，提出了一種具有分離電容器、非二進制加權和多個最低有效位元 (LSB) 冗餘電容器數類比轉換器 (CDAC) 的低功耗 12 位元 SAR ADC。 所提出的具有非二進制加權和多個 LSB 冗餘 CDAC 的 SAR ADC 具有用於糾正由於雜訊和不完整的數位類比轉換器 (DAC) 開關穩定而導致的誤碼決策的最佳機制。 為了減少總電容，12 位元 DAC 的所有電容值均除以 16，並使用並聯電容方案來實現這些非整數電容。 12 位元 SAR ADC 採用 CMOS 0.18μm 1P6M技術製造。 測得的最小（最大）微分非線性和積分非線性分別為 -0.4(0.54) 和 -0.81(0.89) LSB，其中 1 LSB = 0.488 mV。 輸入頻率為 500 kHz、取樣率為 1 MS/s 時，訊號雜訊比和有效位數分別為 69.51 dB 和 11.25 位元。 所提出的 SAR ADC 在取樣率為 1 MS/s 時具有 18.39-fJ/conversion-step的品質因數 (FoM)。

In this study, complementary metal–oxide semiconductor 0.18-μm 1P6M technology was used to fabricate a 16-channel front-end readout chip for radiation sensors. This chip reads the current signal of the radiation sensor and converts this signal into digital serial data by using a nonbinary successive approximation register (SAR) analog-to-digital converter (ADC) with a sampling rate of 1 MS/s and a resolution of 10 bits. The minimum (maximum) differential nonlinearity and integral nonlinearity of this chip were measured to be −0.32 (0.33) and −0.43 (0.37) least significant bits, respectively. At an input frequency of 500 kHz and a sampling rate of 1 MS/s, the sig-nal-to-noise-and-distortion ratio and effective number of bits were determined to be 57.41 dB and 9.24 bits, respectively. The SAR ADC of the developed chip had a figure of merit of 38.9 fJ/conversion step at a sampling rate of 1 MS/s. The developed chip can read input signals with peak currents ranging from 20 to 750 μA, and it can convert analog signals into 10-bit serial-output digital signals. The input dynamic range of the chip is 2–75 pC, its current resolution is 208.3 nA, its area is 1.444 mm × 10.568 mm, and its power consumption per channel is 19 mW. For improving SAR ADC performance, a low-power 12-bit SAR ADC with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed. The proposed SAR ADC with nonbinary-weighted and multiple-LSB-redundant CDACs has an optimal mechanism for correcting the bit error decisions due to noise and incomplete digital-to-analog converter (DAC) switching settling. To reduce the total capacitance, all capacitor values of the 12-bit DAC were divided by 16, and a parallel-series capacitor scheme was used to implement these noninteger capacitors. The 12-bit SAR ADC prototype was fabricated using 0.18-μm 1P6M complementary metal oxide semiconductor technology. The maximal differential nonlinearity and integral nonlinearity were measured as −0.4/0.54 and −0.81/0.89 LSB, respectively, where 1 LSB = 0.488 mV. The signal-to-noise-and-distortion ratio and effective number of bits were 69.51 dB and 11.25 bits, respectively, for the input frequency of 500 kHz and sampling rate of 1 MS/s. The proposed SAR ADC features an 18.39-fJ/conversion-step Figure-of-Merit (FoM) at the sampling rate of 1 MS/s.

[1] P. A. R. Abu, S.-L. Chen,” VLSI implementation of an efficient lossless EEG compression design for wireless body area network,” Applied Sciences, vol. 8, 2018, pp. 1-11.
[2] J.-Z. Jian, T.-R. Ger, H.-H. Lai, C.-M. Ku, C.-A. Chen, P. A. R. Abu, S.-L. Chen,” Detection of myocardial infarction using ECG and multi-scale feature concatenate,” Sensors, vol. 21, 2021, pp. 1-17.
[3] L.-H. Wang, W. Zhang, M.-H. Guan, S.-Y. Jiang, Fan, M.-H.; Abu, P. A. R; Chen, C.-A.; Chen, S.-L.. A low-power high-data-transmission multi-lead ECG acquisition sensor system. Sensors, vol. 19 2019, pp. 1-14.
[4] S.-L. Chen, J. F. Villaverde, H.-Y. Lee, W.-Y. Chung, T.-L. Lin, C.-H. Tseng, K.-A. Lo,” A power-efficient mixed-signal smart ADC design with adaptive resolution and variable sampling rate for low-power applications,” IEEE Sensors Journal, vol. 17,2017, pp. 3461-3469.
[5] S.-L. Chen, M.-C. Tuan, H.-Y. Lee, T.-L. Lin,” VLSI implementation of a cost-efficient micro control unit with an asymmetric encryption for wireless body sensor networks” IEEE Access, vol. 5, 2017, pp. 4077-4086.
[6] S.-L. Chen,” A power-efficient adaptive fuzzy resolution control system for wireless body sensor networks,” IEEE Access, vol. 3, 2015, pp. 743-751.
[7] T.-R. Ger, P.-S. Wu, W.-J. Wang, C.-A. Chen, P. A. R. Abu, S.-L. Chen,” Development of a microfluidic chip system with giant magnetoresistance sensor for high-sensitivity detection of magnetic nanoparticles in biomedical applications,” Biosensors, vol. 13, 2023, pp. 1-9.
[8] H.-L., Kuo, S.-L.,Chen,” Radiation Detector Front-End Readout Chip with Nonbinary Successive Approximation Register Analog-to-Digital Converter for Wearable Healthcare Monitoring Applications" Micromachines 15, no. 1: 143.
[9] C.-K. Liu, W.-Y. Chiang, P.-Z. Rao, P.-H. Hung, S.-L. Chen, C.-A. Chen, L.-H. Wang, P. A. R. Abu, S.-L. Chen,” The uses of a dual-band corrugated circularly polarized horn antenna for 5G systems,” Micromachines, vol. 13, 2022, pp. 1-18.
[10] S. Surti, M. E. Werner, A. E. Perkins, J. Kolthammer, J. S. Karp,” Performance of Philips Gemini TF PET/CT scanner with special consideration for its time-of-flight imaging capabilities,” The Journal of Nuclear Medicine, vol. 48, 2007, pp. 471–480.
[11] R. F. Muzic, J. A. Kolthammer,” PET performance of the Gemini TF: A time-of-flight PET/CT scanner” In Proc. IEEE Nucl. Sci. Symp. Conf. Rec. , vol. 3, 2006, pp. 1940–1944.
[12] N. Ollivier-Henry, W. Gao, N. A. Mbow, D. Brasse, B. Humbert, C. HuGuo, C. Colledani, Y. Hu,” Design and Characteristics of a Full-Custom Multichannel Front-End Readout ASIC Using Current-Mode CSA for Small Animal PET Imaging,” IEEE Transactions on Biomedical Circuits and Systems, vol. 5, 2011, pp. 90-99.
[13] W. Gao, D. Gao, T. Wei, H. Zeng, Y. Duan, S. Lu, L. Shen, W. Xu, Q. Xie, Y. Hu," Design of a Monolithic Multi-Channel Front-End Readout ASIC for LYSO/SiPM-based Small Animal Flat-Panel PET Imaging,” IEEE Nuclear Science Symposium Conference Record 2011, pp. 2447-2450.
[14] N. Schemm, S. Balkır, M. W. Hoffman,” A 4-μW CMOS Front End for Particle Detection Applications,” IEEE Trans. on Circuits And Systems—II: Express Briefs, vol. 57, 2010, pp. 100-104.
[15] W. Gao, D. Gao, C. Hu-Guo, T. Wei, Y. Hu,” Design and Characteristics of an Integrated Multichannel Ramp ADC Using Digital DLL Techniques for Small Animal PET Imaging,” IEEE Transactions on Nuclear Science, vol. 58, 2011, pp. 2161-2168.
[16] L. H. C. Braga, L. Gasparini, L. Grant, R. K. Henderson, N. Massari, M. Perenzoni, D. Stoppa, R. Walker,” A Fully Digital 8×16 SiPM Array for PET Applications With Per-Pixel TDCs and Real-Time Energy Output,” IEEE J. Solid-State Circuits, vol. 49, 2014, pp. 301-314.
[17] Pieter Harpe, et. al, “A 0.20 mm2 3 nW Signal Acquisition IC for Miniature Sensor Nodes in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 51, no. 1, Jan 2016, pp. 240-248.
[18] S.-Y. Kim, et. al, “Design of a High Efficiency DC–DC Buck Converter With Two-Step Digital PWM and Low Power Self-Tracking Zero Current Detector for IoT Applications,” IEEE Trans. Power Electron., vol. 33, no. 2, Feb. 2018, pp. 1428–1439.
[19] J.-E. Park, Y.-H. Hwang, and D.-K. Jeong, “A 0.4-to-1 V Voltage Scalable ΔΣADC With Two-Step Hybrid Integrator for IoT Sensor Applications in 65-nm LP CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 64, no. 12, Dec. 2017, pp. 1417–1421.
[20] Junbo Shim, et. al, “An Ultra-Low-Power 16-Bit Second-Order Incremental ADC With SAR-Based Integrator for IoT Sensor Applications,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 65, no. 12, Dec. 2018, pp. 1899–1903.
[21] Haoming Xin, et. al,” A 174 pW–488.3 nW 1 S/s–100 kS/s All-Dynamic Resistive Temperature Sensor With Speed/Resolution/Resistance Adaptability,” IEEE Solid-State Circuits Let., vol. 1, no. 3, Mar 2018, pp. 70-73.
[22] Ming Ding, et. al,” A Hybrid Design Automation Tool for SAR ADCs in IoT,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 26, no. 12, Dec 2018, pp. 2853–2862.
[23] Z. Zhang, et. al,” A Dynamic Tracking Algorithm Based SAR ADC in Bio-Related Applications,” IEEE Access, vol. 6, pp. 62166–62173, Nov. 2018.
[24] W.-M. Chen, et. al,” A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control,” IEEE J. Solid-State Circuits, vol. 49, no. 1, Jan 2014, pp. 232-247.
[25] J. L. McCreary and P. R. Gray, “All-MOS charge redistribution analog-to-digital conversion techniues—Part I,” IEEE J. Solid-State Circuits, vol. SC-10, no. 6, Dec. 1975, pp. 371-379.
[26] Brian P. Ginsburg, and Anantha P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS With Split Capacitor Array DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 4, Apr. 2007, pp. 739-747.
[27] C. C. Liu, et. al, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, Apr. 2010, pp. 731-740.
[28] Y. Zhu, et. al, “A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, Jun 2010, pp. 1111-1121.
[29] Erkan Alpman, et. al,” A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS,” in IEEE ISSCC Dig. Tech. Papers, 2009, pp. 76-77a.
[30] Nikolas P. Papadopoulos, et. al,” Toward Temperature Tracking With Unipolar Metal-Oxide Thin-Film SAR C-2C ADC on Plastic,” IEEE J. Solid-State Circuits, vol. 53, no. 8, Aug 2018, pp. 2263-2272.
[31] Andrea Agnes, et. al, ” A 9.4-ENOB 1V 3.8μW 100kS/s SAR ADC with Time- Domain Comparator,” in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 246-247.
[32] J. Shen, A. Shikata, et. al, “A 16-bit 16MS/s SAR ADC with On-Chip Calibration in 55nm CMOS,” in Proc. Symp. VLSI Circuits (VLSIC), Kyoto, Japan, Jun. 2017, pp. C282-C283.
[33] J. Y. Um, et. al, “A Digital-Domain Calibration of Split-Capacitor DAC for a Differential SAR ADC Without Additional Analog Circuits,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 60, no. 11, Nov 2013, pp. 2845-2856.
[34] Yanfei Chen, et. al,” Split Capacitor DAC Mismatch Calibration in Successive Approximation ADC,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), Sep. 2009, pp. 279–282.
[35] C. C. Liu, C. H. Kuo, and Y. Z. Lin, “A 10 bit 320 MS/s Low-Cost SAR ADC for IEEE 802.11ac Applications in 20 nm CMOS,” IEEE J. Solid-State Circuits, vol. 50, no. 11, Nov 2015, pp. 2645-2654.
[36] Pieter J. A. Harpe, et. al, Guido Dolmans, Harmke de Groot, “A 26μW 8 bit 10 MS/s Asynchronous SAR ADC for Low Energy Radios,” IEEE J. Solid-State Circuits, vol. 46, no. 7, Jul 2011, pp. 1585-1595.
[37] R. Xu, et. al,” A 1/2.5 inch VGA 400 fps CMOS Image Sensor With High Sensitivity for Machine Vision,” IEEE J. Solid-State Circuits, vol. 49, no. 10, Oct 2014, pp. 2342-2351.
[38] S. H. Wan, et. al, C. P. Huang, G. J. Ren, K. T. Chiou, C. H. Ho, “A 10-bit 50-MS/s SAR ADC with techniques for relaxing the requirement on driving capability of Reference voltage buffers,” in Proc. IEEE A-SSCC, 2013, pp.293-296.
[39] X.Y. Tong, et. al,” D/A conversion networks for high-resolution SAR A/D converters,” Electron. Let., vol. 47, no. 3, 2011, pp. 169-171.
[40] Michael Inerfield, et. al,” An 11.5-ENOB 100-MS/s 8mW dual-Reference SAR ADC in 28nm CMOS,” in Proc. Symp. VLSI Circuits (VLSIC), Jun. 2014, pp. 1-2.
[41] H. Zhang, et. al,” A 0.6-V 10-bit 200-kS/s SAR ADC With Higher Side-Reset-and-Set Switching Scheme and Hybrid CAP-MOS DAC,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 11, Nov 2018, pp. 3639-3650.
[42] C. C. Liu, et. al, ” A 1V 11fJ/conversion-step 10bit 10MS/s asynchronous SAR ADC in 0.18µm CMOS,” in Proc. Symp. VLSI Circuits (VLSIC), Jun. 2010, pp. 241-242.
[43] C. C. Liu, et. al,” A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation,” in IEEE ISSCC Dig. Tech. Papers, 2010, pp. 386-387.
[44] Franz Kuttner, “A 1.2V 10b 20MSample/s Non-Binary Successive Approximation ADC in 0.13μm CMOS,” in IEEE ISSCC Dig. Tech. Papers, 2002, pp. 176-177.
[45] W. Liu, P. Huang, and Y. Chiu, “A 12-bit, 45-MS/s, 3-mW Redundant Successive-Approximation-Register Analog-to-Digital Converter With Digital Calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 11, Nov 2011, pp. 2661-2672.
[46] D. Li, Z. Zhu, R. Ding, and Y. Yang,” A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 65, no. 11, Nov 2018, pp. 1524-1528.
[47] Vito Giannini, et. al,” An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS,” in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 238-239.
[48] H.-L. Kuo, C.-W. Lu, P. Chen,” An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC,” IEEE Access, vol. 9, 2021, pp. 5651–5669.
[49] H.L. Kuo, C.-W. Lu, S.-G. Lin, D.-C. Chang,” A 10-bit 10 MS/s SAR ADC with the reduced capacitance DAC,” In Proc. International Symposium on Next-Generation Electronics (ISNE), Hsinchu, Taiwan, 4–6, May, 2016, pp. 1–2.
[50] B. Razavi,” Design of Analog CMOS Integrated Circuit,” Boston, McGraw-Hill, 2006, pp.209, pp. 378-381, 465.
[51] S. A. Mahmoud, A. M. Soliman,” The Differential Difference Operational Floating Amplifier: A New Block for Analog Signal Processing in MOS Technology,” IEEE Trans. on Circuits And Systems—II: Analog and Digital Signal Processing, vol. 45, 1998, pp. 148-158.
[52] Naveen Verma, and Anantha P. Chandrakasan, “ An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes,” IEEE J. Solid-State Circuits, vol. 42, no. 6, Jun 2007, pp. 1196-1205.
[53] A.M. Abo, and P.R. Gray,” A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, May 1999, pp. 599-606.
[54] Y.-J. Chen, K.-H. Chang, and C.-C. Hsieh,” A 2.02–5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC With Time-Domain Quantizer in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 51, no. 2, Feb 2016, pp. 357-364.
[55] Michiel van Elzakker, et. al,” A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC,” in IEEE ISSCC Dig. Tech. Papers, 2008, pp. 243-245.
[56] P.M. Figueiredo, and J.C. Vital,” Kickback noise reduction techniques for CMOS latched comparators,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 7, Jul 2006, pp. 541-545.
[57] H.W. Kang, H. K. Hong, W. Kim, and S. T. Ryu , “A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme,” IEEE J. Solid-State Circuits, vol. 53, no. 9, Sep 2018, pp. 2584-2594.
[58] C. W. Hsu, et. al,” A 12-b 40-MS/s Calibration-Free SAR ADC,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 3, Mar 2018, pp. 881-890.
[59] Yi Shen, Z. Zhu, S. Liu, and Y. Yang,” A Reconfigurable 10-to-12-b 80-to-20-MS/s Bandwidth Scalable SAR ADC,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 1, Jan 2018, pp. 51-60.
[60] Y. Hirai, et. al, “A Biomedical Sensor System With Stochastic A/D Conversion and Error Correction by Machine Learning,” IEEE Access, vol. 7, Mar. 2019, pp. 21990–22001.
[61] Naveen Verma, and Anantha P. Chandrakasan,“ An Ultra Low Energy 12-bit Rate-Resolution Scalable SAR ADC for Wireless Sensor Nodes,” IEEE J. Solid-State Circuits, vol. 42, no. 6, Jun 2007, pp. 1196-1205.
[62] Shanthi Pavan, Richard Schreier, Gabor C. Temes, “Understanding Delta-Sigma Data Converters,” 2017, Wiley-IEEE Press, pp. 140-162.