串音效應(crosstalk effect)起因於平行電線間的耦合電容(coupling ca-pacitance)；且隨著製程的持續進步，串音效應也日益受到重視。根據模擬結果顯示，在十奈米(10nm)的製程下，消除所有串音可改善22.62%至83.47%的延遲(delay)。因此，許多文獻都致力於研究如何減少串音。

但在這些已發表的文獻中，有許多方法需要額外的硬體資源，例如插入保護線(shield insertion)、編碼/解碼器(encoder/decoder)等；而另外一些討論低功率(low power)的文獻則沒有考慮到串音效應。

在這篇論文中，我們提出了一個創新的指令操作碼(operation code)與功能碼(functional code)設計方法，可減低指令匯流排(instruction bus)上的串音與動態功率(dynamic power)。

本設計方法主要包含四個步驟：
一、 目標測試程式的取樣(target benchmark profiling)
二、 關連圖與資源圖的產生(adjacency/resource graph generation)
三、 完全圖的切割(clique partition)
四、 代碼的指派(code assignment)

實驗結果顯示我們的方法分別可以減少32.70%至67.10%的4C串音、21.93%至36.32%的3C串音，以及4.63%至6.69%的位元變動(bit transition)。

Crosstalk comes from coupling capacitance between parallel wires, and is getting more and more important as technologies continue to shrink. According to simulation result, eliminating all crosstalk in 10nm technology
can bring delay reduction ranging from 22.62% to 83.47%. Many researches have been published to alleviate crosstalk. However, some of them, like shield insertion and encoder/decoder, incur extra hardware overhead, and
others focusing on low power do not handle crosstalk.

In this thesis, we propose an innovative algorithm of operation and functional codes assignment to minimize crosstalk and reduce dynamic power on instruction buses. Our
algorithm °ow includes target benchmark pro‾ling, adjacency and resource graph generation, clique partition, and code assignment. Experimental results show that our algorithm can decrease 4C crosstalk from 32.70% to 67.10%, 3C crosstalk from 21.93% to 36.32%, and bit transitions from 4.63% to 6.69%, respectively.

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