新型氮氧化鈦接觸電阻式隨機存取記憶體與其載子傳輸模型

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研究生：	曾元亨 Tseng, Yuan-Heng
論文名稱：	新型氮氧化鈦接觸電阻式隨機存取記憶體與其載子傳輸模型 A New TiON Based Contact Resistive Random Access Memory (CRRAM) and Its Carrier Transport Model
指導教授：	林崇榮 Lin, Chrong-Jung 金雅琴 King, Ya-Chin
口試委員:	張彌彰連振炘張孟凡莊紹勳蔡銘進翁烔城金雅琴林崇榮
學位類別：	博士 Doctor
系所名稱：	電機資訊學院 - 電子工程研究所 Institute of Electronics Engineering
論文出版年：	2012
畢業學年度：	100
語文別：	英文
論文頁數：	126
中文關鍵詞：	電阻式隨機存取記憶體、接觸電阻式隨機存取記憶體、記憶體、隨機電報雜訊、電阻切換模型
外文關鍵詞：	RRAM, CRRAM, memory, RTN, resistive switching model
相關次數：	點閱：3 下載：0
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近來為了應付龐大的電子資料之保存，因此相對地須使現存的超大型積體電路記憶元件具有較佳的操作性能以及可靠度等之需求與日俱增，但當製程技術越過65奈米的世代時，將成為巨大的挑戰。興新的記憶體中可近乎這些需求的標準包括磁阻式記憶體(MRAM)，像變化記憶體(PCM)和電阻式記憶體(RRAM)皆是大有可為的參考候選，甚至以獨立化商品型式與嵌入式記憶體的應用為目標。
在本論文之中，成功地展示與驗證一完全相容於90 nm互補式金氧半(CMOS)邏輯製程技術下之新穎的接觸電阻式記憶體(CR-RAM)，這元件的記憶端點是將TiN/TiON/SiO2材料堆疊於鎢接觸點(W contact)與N+矽之間以實現之。此外，它呈現了絕佳的元件特性例如：快速編程、製程簡單、免疫於重複寫入之影響、具非揮發性等，且資料的保存力於150 °C的測試溫度下更是超越了1 000小時以上。藉由電流偏壓法測定1T+1R (一電晶體一電阻) CR-RAM 自我限流之觀察，更進一步支持重置(reset)電流可以藉著利用字元線去控制設置(set)電流而使之減小。為了推展CR-RAM的切換機制，起因於電子捕捉與釋放產生的隨機電報雜訊(RTN)之量測法被用於探討CR-RAM堆疊層之特性。由RTN模型的輔助之下，量測而得的資料可被用於參數的萃取與分析，以致最終發展出一陷阱引發電阻切換之預測模型。

Increasing demand for better cell performance and reliability in VLSI memories is currently a great challenge beyond the 65 nm technology node. Emerging memories such as MRAM (Magnetoresistive Random Access Memory), PCM (Phase Change Memory), and RRAM (Resistive Random Access Memory) are promising candidates to meet these requirements, and are even targeted at stand-alone and embedded memory applications.
This dissertation presents a novel contact RRAM (CR-RAM) realized by stacking TiN/TiON/SiO2 between W contact and N+ silicon, which is fully compatible with 90 nm CMOS logic technology. The proposed RRAM exhibits excellent performance in terms of a fast program speed, easy fabrication, and immunity to overwrite and non-volatility. Data retention is significantly over 1 000 hours under 150 °C baking conditions. An investigation of the self-compliance of the One Transistor 1T+1R CR-RAM (One Resistor Contact Resistive Random Access Memory) using the current bias method confirms that the reset current can be reduced by the word-line (WL) controlled set current. The random telegraph noise (RTN) generated by electron trapping/de-trapping on the stacking layers was also investigated to determine the CR-RAM switching mechanism. The RTN model makes it possible for parameter extraction from the measured data. Analyzing the extracted parameters and the measured results lead to a proposed trap-induced resistive switching model.

Abstract    i
摘要    ii
Acknowledgement    iii
Table of Contents    iv
List of Tables    vii
List of Figures    viii
Chapter 1 Introduction    1
1 Preface    1
2 Motivation    2
3 Dissertation Organization    3
Chapter 2 Next-Generation Non-Volatile Memories    4
1 Introduction    4
2 Phase Change Memory (PCM)    4
3 Magnetoresistive Random Access Memory (MRAM)    5
4 Resistive Random Access Memory (RRAM)    6
4.1. Self-Accelerated Thermal Dissolution Model    7
4.2. Ion-Transport-Recombination Model    8
5 Summary    8
Chapter 3 Contact Resistive Random Access Memory (CR-RAM) Devices    17
1 Introduction    17
2 Development of Contact Resistive Random Access Memory Cell    18
2.1 Cell Layout and Structure    18
2.2 CR-RAM contact sizing Effect    19
2.3 Operation Principle for Set and Reset    20
3 Programmable Contact Sizing Effect    21
3.1 DC Characteristics for CR-RAM Cells    22
3.2 CR-RAM Characterization by Pulse Operation    23
4 Resistance and WL Voltages    24
6 Summary    24
Chapter 4 The Word-Line Effect, Operation 
Optimization, and Reliability of 1T+1R CR-RAM    44
1 Introduction    44
2 Designation of the Selection Unit for CR-RAM    45
2.1 Unipolar Switching Characteristics    45
2.2 Measurement of the 1Diond+1Resistor Structure    45
2.3 Measurement of the 1Transistor+1Resistor Structure    46
3 Word-Line and Source-Line Effects on CR-RAM Resistance    47
3.1 How Set Word-Line Voltage Affects LRS    47
3.2 HRS Affected by Word-Line and Source-Line Voltages    49
4 Reliability Issues    49
4.1 Overwriting and Set/Reset Disturb Test    49
4.2 Endurance and Baking Test    49
4 Summary    50
Chapter 5 Random Telegraph Signal (RTS) Models in CR-RAM Device    61
1 Introduction    61
2 Two-Level Current Fluctuations    62
2.1 Fluctuation Factor    62
2.2 Lifetimes and Fluctuation Amplitude    63
2.3 Mean Capture and Emission Time    64
3 Random Telegraph Noise (RTN) Models    65
3.1 Trap Energy    66
3.2 Activation Energy    67
4 Effective Trap Depth and Leakage Area    70
4.1 Trap Depth    71
4.2 Effective Area of Leakage Path    71
7 Summary    72
Chapter 6 Modeling of Electron Conduction and Resistive Switching in CR-RAM Devices as Random Telegraph Noise    89
1 Introduction    89
2 CR-RAM Resistance Characteristics and Temperature Effect    90
2.1 Nonpolar Resistive Switching Characteristic    90
2.2 Trap-Induced RTS in CR-RAM Dielectric    91
2.3 Noise Power Spectrum    91
2.4 Space Charge Limited Current (SCLC) Model    92
2.5 Temperature Effect on Resistance and Instability    92
3 Random Telegraph Noise (RTN) Analysis and Discussion    93
3.1 Forward and Reverse Operation    93
3.2 WL Effect    94
4 Trap-Induced Resistive Switching Model    95
5 Zeff on Forward and Reverse Measurements    95
5.1 Temperature Effect on Zeff    95
5.2 Trap Characterization on Forward and Reverse Measurements    96
6 Summary    97
Chapter 7 Conclusion    115
1 Conclusion    115
References    117
Vita    125
 

                                

Chapter 1

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Chapter 2

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Chapter 3

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[9] K. Kinoshita, K. Tsunoda, Y. Sato, H. Noshiro, S. Yagaki, M. Aoki, and Y. Sugiyama, ” Reduction in the reset current in a resistive random access memory consisting of NiOx brought about by reducing a parasitic capacitance,” in Appl. Phys. Lett., 93, 033506 (2008).
[10] K. Kinoshita, K. Tsunoda, Y. Sato, H. Noshiro, Y. Yamazaki, T. Fukano, S. Yagaki, M. Aoki, Y. Sugiyama, ” Reduction of Reset Current in NiO-ReRAM Brought about by Ideal Current Limiter,” in IEEE NVSMW, pp. 66-67, Aug. 2007.
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Chapter 4

[1] D. Lee, D.-J. Seong, H. J. Choi, I. Jo, R. Dong, W. Xiang, S. Oh, M. Pyun, S.-O Seo, S. Heo, M. Jo, D.-K Hwang, H. K. Park, M. Chang, M. Hasan and H. Hwang, “ Excellent uniformity and reproducible resistance switching characteristics of doped binary metal oxides for non-volatile resistance memory applications,” in IEDM Tech. Dig., 2006.
[2] H. Sim, J. Choi, D. Lee, M. Chang, D. Choi, Y. Son, E.-H. Lee, W. Kim, Y. Park, I.-K. Yoo and H. Hwang, “ Excellent Resistance Switching Characteristics of Pt/SrTiO3 Schottky Junction for Multi-bit Nonvolatile Memory Application,” in IEDM Tech. Dig., pp 758-761, 2005.
[3] K. Tsunoda, K. Kinoshita, H. Noshiro, Y. Yamazaki, T. Jizuka, Y. Ito, A. Takahashi, A. Okano, Y. Sato, T. Fukano, M. Aoki, and Y. Sugiyama, “ Low Power and High Speed Switching of Ti-doped NiO RRAM under the Unipolar Voltage Source of less than 3V,” in IEDM Tech. Dig., pp. 767-770, 2007.
[4] H. Y. Lee, P. S. Chen, T. Y. Wu, Y. S. Chen, C. C. Wang, P. J. Tzeng, C. H. Lin, F. Chen, C. H. Lien, and M.-J. Tsai, ” Low Power and High Speed Bipolar Switching with A Thin Reactive Ti Buffer Layer in Robust HfO2 Based RRAM,” in IEDM Tech. Dig., 2008.
[5] Y. H. Tseng, C.-E. Huang, C.-H. Kuo, Y.-D. Chih, C. J. Lin, “High Density and Ultra Small Cell Size of Contact RRAM (CR-RAM) in 90nm CMOS Logic Technology and Circuits,” in IEDM Tech. Dig., pp.109-112, 2009.
[6] S. Seo, M. J. Lee, D. H. Seo, E. J. Jeoung, D.-S. Suh, Y. S. Joung, and I. K. Yoo I. R. Hwang, S. H. Kim, I. S. Byun, J.-S. Kim, J. S. Choi and B. H. Parka, “Reproducible resistance switching in polycrystalline NiO films,”in Appl. Phys. Lett., vol. 23, no. 23, pp. 5655, Dec. 2004.
[7] D. C. Kim, S. Seo, S. E. Ahn, D.-S. Suh, M. J. Lee, B.-H. Park, and I. K. Yoo, I. G. Baek, H.-J. Kim, E. K. Yim, J. E. Lee, S. O. Park, H. S. Kim, U.-I. Chung, J. T. Moon, and B. I. Ryu, ” Electrical observations of filamentary conductions for the resistive memory switching in NiO films,” in Appl. Phys. Lett., 88, 202102 (2006).
[8] U. Russo, D. Ielmini, C. Cagli and A. L. Lacaita, “Filament conduction and reset mechanism in NiO-based resistive-switching memory (RRAM) devices,” in IEEE Trans. Electron Devices, vol. 56, no. 2, pp. 186-192, Feb. 2009.
[9] K. Kinoshita, K. Tsunoda, Y. Sato, H. Noshiro, S. Yagaki, M. Aoki, and Y. Sugiyama, ” Reduction in the reset current in a resistive random access memory consisting of NiOx brought about by reducing a parasitic capacitance,” in Appl. Phys. Lett., 93, 033506 (2008).
[10] K. Kinoshita, K. Tsunoda, Y. Sato, H. Noshiro, Y. Yamazaki, T. Fukano, S. Yagaki, M. Aoki, Y. Sugiyama, ” Reduction of Reset Current in NiO-ReRAM Brought about by Ideal Current Limiter,” in IEEE NVSMW, pp. 66-67, Aug. 2007.
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Chapter 5

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Chapter 6

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[3] U. Russo, D. Ielmini, C. Cagli, A. L. Lacaita, S. Spiga, C. Wiemer, M. Perego and M. Fanciulli, “Conductive-filament switching analysis and self-accelerated thermal dissolution model for reset in NiO-based RRAM,” in IEDM Tech. Dig., pp 775-778, 2007.
[4] N. Xu, B. Gao, L.F. Liu, B. Sun, X.Y. Liu, R.Q. Han, J.F. Kang and B. Yu, ”A unified physical model of switching behavior in oxide-based RRAM,” IEEE Symposium on VLSI Tech., pp 100-101, 2008.
[5] B. Gao, S. Yu, N. Xu, L. F. Liu, B. Sun, X. Y. Liu, R. Q. Han, J. F. Kang, B. Yu, Y. Y. Wang, “Oxide-based RRAM switching mechanism: A new ion-transport-recombination model” in IEDM Tech. Dig., 2008.
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