全數位式時脈與資料回復電路相較於傳統式的時脈與訊號回復電路，有著更好抗雜訊的能力且對製程、電壓及溫度變異(Process,Voltage,Temperature Variation ,PVT Variation)則沒有那麼敏感，由於先進製程的演進，電路晶片設計可以更容易隨著製成一起縮小面積。
本論文主要實現應用於10-GHz全速率之時脈與回復電路，其中本論文所使用的相位偵測器為二進位相位偵測器，其中電路多了偵測隨機輸入資料是否發生轉態的訊號，方便後面的數位迴路濾波器進行運算，而數位迴路濾波器則是採用累加器去完成，且在比例路徑加了SR栓鎖器，避免在遇到連續相同碼時，時脈與資料回復電路之時脈訊號發生改變，導致位元錯誤率的上升，而數位控制振盪器則是採用LC式振盪器，使其相位雜訊能夠好一點，讓最後的抖動容忍度能更加的完美。
論文開頭則是先介紹高速串列訊號傳輸的架構，並依序對其不理想效應進行探討，並對接收端非常重要的眼圖進行講解，接著介紹時脈與資料回復電路的架構以及該電路所需要注意的指標，然後在對本篇論文電路進行數學上的分析，並探討穩定度的問題，最後則是詳細的去介紹所使用的每個子電路特性與操作並進行最後附上整個電路的結果與布局，而本論文使用TSMC 65nm 1P9M CMOS製程，且供應電壓為1.2V的環境下去實現全速率全數位時脈與資料回復電路。輸入資料為10 Gbps PRBS32，也因為是全速率操作，所以還原時脈也是 10Ghz，整體系統功耗為12.72mW。

Compared with the traditional clock and data recovery circuit, the all-digital clock and data recovery circuit has better anti-noise ability and is less sensitive to process, voltage and temperature variation . Not so sensitive, because of the evolution of advanced processes, the circuit chip design can more easily shrink in area along with the fabrication.
This paper mainly realizes the clock and recovery circuit applied to 10-GHz full rate. The phase detector used in this paper is a binary phase detector, and the circuit has more functions to detect whether the random input data has transition. The signal is convenient for the subsequent digital loop filter to perform the operation, and the digital loop filter is completed by the accumulator, and the SR latch is added to the proportional path to avoid the clock and data recovery when encountering the same continuous code. The clock signal of the circuit changes, which leads to an increase in the bit error rate. The digital controlled oscillator uses an LC oscillator, so that the phase noise can be better, and the final jitter tolerance can be more perfect.
At the beginning of the paper, the structure of high-speed serial signal transmission is introduced, and its non-ideal effects are discussed in sequence, and the very important eye diagram at the receiving end is explained, and then the structure of the clock and data recovery circuit and the circuit are introduced. The indicators that need to be paid attention to, and then mathematically analyze the circuit of this paper, and discuss the problem of stability, and finally introduce the characteristics and operations of each sub-circuit used in detail, and finally attach the results of the entire circuit. In this paper, the TSMC 65nm 1P9M CMOS process is used, and the supply voltage is 1.2V to realize the full-rate full-digital clock and data recovery circuit. The input data is 10 Gbps PRBS32, and because it is full-rate operation, the restoration clock is also 10Ghz, the overall system power consumption is 12.72mW。

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