製造業的目標一直都在於降低產品的變異，並提高良率來達到產量的上升，半導體產業也不外如是，初期靠著線上檢驗和管制，以及事後的電性參數測試來達到及時改進和下一次調整的目標，然而在進入奈米時代卻需要回溯到電路佈局設計做配合和改變，以防止產品在製造中因敏感性的飄盪而使得良率不齊。快速熱處理製程是電晶體與電容形成的重要步驟之ㄧ，也是摻雜活化的重要媒介，除此之外熱處理技術的優劣更影響到短通道效應以及接面深度，直接牽連良率、效能和可靠度，毫秒高溫退火是目前被業界廣為使用的熱處理方法，然而在極高的溫度和極短的退火時間之下，晶片容易因為圖形效應而產生溫差嚴重不均的現象，造成電性參數的良率降低，因此本研究提出時變參數PSO來達到虛擬填充的最佳化，改變原始佈局設計的等效吸收率，進而達到降低整體佈局溫差的目的。本研究以某知名半導體廠提供的密度及吸收率資料，取出不同設計大小的佈局作為實證研究，由結果顯示本研究方法可以有效改善55%以上的溫度差異，在更大的佈局上進行填充時能有效的達到更穩定的效率以及更快速的運算時間。

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