在本論文中，我們將探討在硬體模擬器的部份連結架構( partial crossbar interconnection structure )中，有關於切線配置( net assignment )的問題。 對於切線配置的問題，若所有的切線都只有兩端點( two-terminal )時，此問題確定可在polynomial time內解決；然而若是多端點( multi-terminal )的切線，就變成了NP-complete的問題。之前有其它的研究提出了一個簡單的heuristic方法來解決切線配置的問題，但該實驗結果顯示其有所不足，因此我們提出一個完整演算法( exact algorithm )來解決切線配置問題。只要該問題有解，本演算法就能找出其解。 然而完整演算法太過耗時，因此我們提出一個二階段解決法。在第一階段裡，我們先呼叫一個較有效率的heuristic來做切線配置；若此heuristic無法解得答案，我們就交由第二階段的完整眼算法來做。
第一章 簡介：近年來，現場可程式閘陣列積體電路( Field Programmable Gate Array, FPGA )被廣泛地應用在電路原型製作( prototyping )以及硬體模擬系統( emulation system )上。在模擬系統方面，其連結架構大致可分為二類：第一類為FPGA直接與其它的FPGA相連接；第二類為FPGA透過現場可程式連結晶片( Field Programmable Interconnection Chip, FPIC )來和其它的FPGA做連結。本論文針對第二類連結架構，並使用部份連結結構( partial crossbar interconnection structure )來探討其切線配置的問題。

第二章 硬體模擬系統：目前市場上可見的硬體模擬系統中，需要用FPIC來做切線連結的有APTIX, BORG, Realizer…等系統。 而一般多會使用Aptix FPIC, IQ160, TI Crossbar, FPGA…等元件來做為連接切線的FPIC。

第三章 連結架構：本章詳細介紹部份連結架構( partial crossbar interconnection structure )，並研討當所有的切線( net ) 只有兩個端點( two-terminal )時，可利用Clos network和edge-coloring of bipartite graph的觀念，來證明切線配置( net assignment )的問題可在polynomial time內解決；而當其切線是多端點( multi-terminal )時，切線配置問題則變成NP-complete。

第四章 切線配置問題： 一般真實的電路中其切線多為多端點切線，因此若把這些多端點切線轉換成二端點切線雖然可在polynomial time內完成切線配置，卻也失去原問題的真正意義。因此直接對多端點切線來做切線配置是較實際的。 然而之前對多端點切線所提出的簡單切線配置方法有許多瑕疵，因此我們先審視先前提出的heuristics做探討，並提出一個二階段解決方法：在第一階段先以較具時效性的heuristic來做切線配置，如果它不能得到解，就交由第二階段的完整演算法( exact algorithm )來完成切線配置的動作。

第五章 完整演算法：在本章中我們提出一個完整演算法( exact algorithm )來做多端點切線的切線配置動作。只要原問題有解，本演算法必可找到其解。在完整演算法中，我們將原問題模型成非線性不等式，運用一些矩陣運算的方法，本演算法可以找到其解。

第六章 實驗結果：實驗結果顯示，只要原問題有解，完整演算法可以找出其解。對於 heuristic 方法無法解的例子，完整演算法都可以得到解。

第七章 結論：本論文詳細探討硬體模擬系統中，部份連結架構的切線配置，並發展了一個完整演算法來解決多端點切線的切線配置。

In this thesis, we will study the net assignment problem in partial crossbar interconnection architecture [1,4]. Net assignment of two-terminal nets in this interconnection structure is guaranteed to be completed in polynomial time. However, net assignment of multi-terminal nets becomes NP-complete. Previous paper [1] has proposed a simple heuristic to perform net assignment for multi-terminal nets. Its results showed that it failed to complete routing all nets for many cases. It is inadequate to have net assignment algorithm which does not guarantee an exact solution, for the failure of interconnecting FPGAs will result in the failure of whole mapping to the computing engine or redoing the previous steps, e.g., partitioning of circuits. Therefore, we will propose an exact algorithm to solve the net assignment problem. The exact algorithm will find a solution if there exists one. However, the exact algorithm may take exponential time. Accordingly, a two-phase approach will be taken in this research. A time-efficient heuristic method [14,15] will be called first. The exact solver will be called only if the heuristic fails to deliver a solution.

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