摘要
VLSI製程技術持續以元件微縮為目標，在CMOS等效氧化層厚度上以被要求微縮至1nm以下。然而，由於以二氧化矽做為介電層微縮到1.5nm以下會導致嚴重的漏電流問題，為了元件持續微縮，改採用高介電常數材料取代二氧化矽做為介電層，但高介電材料與矽基板為非理想接面、界面氧化層的增生使EOT微縮不易與載子遷移率下降，皆是使用高介電材料介電層所帶來的一些新挑戰。
第一部分以鉿金屬層與氧化鉿搭配鈦金屬層作為高介電層形成閘極介電層，藉此提高介電層之介電係數，改變鉿金屬層的cycle數和氧化鉿的厚度，觀察鉿金屬層和氧化矽反應的效果，以達到微縮EOT的目的。在氧化鉿和二氧化矽之間，加一層數個原子層厚度的鉿金屬層，再加上適當溫度的PDA，期待能鉿金屬層更容易與二氧化矽反應，與促進晶型的改變。且討論不同鉿金屬層的cycle數和氧化鉿的厚度，期望找出最佳化的鉿金屬層的cycle數和氧化鉿的厚度，使得鉿金屬層往下與二氧化矽反應，形成高介電HfSiOX interface layer。
第二部分以鉿金屬層與氧化鉿作為高介電層，搭配不同溫度之PDA，藉此觀察鉿金屬層和氧化矽反應的效果，研究最適合鉿金屬的反應溫度。另外，以鉿金屬層與氧化鉿經過不同PDA溫度，且搭配更高介電常數金屬-鈦作為高介電層形成閘極介電層，藉此提高介電層之介電常數，且從不同PDA溫度退火中，觀察出鉿金屬和氧化矽反應程度與鈦經過PDA之擴散深度的影響。因為Ti容易擴散的緣故，造成interfacial layer的增生和提升k值，如何在兩者之間取得平衡，關鍵就在值PDA的溫度；經由PDA 600℃，適當使得Hf layer往下搶氧，因此可進一步控制Ti擴散的程度，使之不至於造成過多interfacial layer的增生，則可達到EOT的微縮；但是在遲滯量與元件可靠度方面，也因參雜入Ti而有變差的趨勢。
第三部分本章節以化雙氧水形成學氧化層經高溫退火，再以400:1稀釋之氫氟酸蝕刻至不同厚度形成高品質介面層，討論不同厚度之二氧化矽界面氧化層堆疊高介電材料介電層，對電性所造成的影響。再者討論化學氧化層有無經高溫退火，作為界面層，對電性所造成的影響。比較SRPO與Chemical oxide 在電性與可靠度的差異。實驗結果發現，SRPO在遲滯量與元件可靠度上皆有較佳的特性，這應與經高溫氮氣退火使得氧化層應力釋放與氮氣修補氧化層缺陷有關，但是SRPO會使得Hf layer無法往下消耗interfacial layer之特性，讓k直無法有效提升。在比較Chemical oxide與SRPO兩種interfacial layer上，優點是減少SRPO的厚度可進一步微縮EOT，而元件特性無明顯的惡化，但缺點無法讓Hf layer法往下消耗interfacial layer，使HfO2形成tetragonal的晶型。從製程難易和結果綜合探討Chemical oxide搭配Hf layer是目前最佳的氧化層。

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