研究生: |
陳伯煇 Po-Hui Chen |
---|---|
論文名稱: |
Multiprocessor System-on-Chip Profiling Architecture: Design and Implementation 多處理器系統單晶片量測架構設計與實作 |
指導教授: |
金仲達
Chung-Ta King |
口試委員: | |
學位類別: |
碩士 Master |
系所名稱: |
電機資訊學院 - 資訊系統與應用研究所 Institute of Information Systems and Applications |
論文出版年: | 2008 |
畢業學年度: | 96 |
語文別: | 英文 |
論文頁數: | 66 |
中文關鍵詞: | 多核心 、嵌入式系統 、效能量測 、架構 、設計 、監控 |
外文關鍵詞: | Multi-core, Multi-processor, Embedded system, profiling, architecture, monitor |
相關次數: | 點閱:4 下載:0 |
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隨著嵌入式系統複雜度的提升與技術的進步,多處理器系統單晶片成為嵌入式架構設計的一項新趨勢。因此,有效率地監測與找出效能瓶頸的量測方法更顯其重要性。目前大多數的開放原始碼多處理器單晶片雛型系統並沒有具備特殊硬體支援提供程式設計人員分析或最佳化應用程式,此外,隨著單晶片內的處理器數量的增加使得效能量測更加困難與複雜。
本論文提出了一個多處理器系統單晶片效能量測架構(MPPA),幫助程式設計人員分析底層系統中的硬體事件。這個架構主要的特色為支援多處理器系統,能同時監控所有的處理器以及其他系統元件。此外,這個輕量級的架構有別於一般的設計需要額外新增硬體指令或特殊硬體溝通介面,MPPA並不需要大幅修改原始架構,達到精簡的目的。我們實做這個量測架構並整合LEON3開放原始碼嵌入式系統平台並於Xilinx ML501 FPGA實驗板驗證這個多處理器嵌入式系統。實驗結果顯示我們提出的量測架構確實能取得系統底層硬體事件,幫助程式設計人員更容易地分析了解應用程式行為,並且在符合精簡、有彈性與小幅修改的需求條件下,提供更多的資訊來找出系統效能瓶頸。
With the growing complexity and the improvement in embedded systems, MPSoC (Multiprocessor System-on-Chip) has become a new trend of embedded architecture design. As a result, the mechanisms of performance monitoring to effectively monitor these systems and find out the performance bottlenecks are in great need. Currently, most of the open source MPSoC prototyping systems do not have special hardware supports for programmers to analyze, or to tune their target applications. Besides, with the increasing number of processors within a single chip, it would be more difficult and complex to do performance measurement.
In this thesis, we propose a multiprocessor profiling architecture, ‘MPPA’, which helps programmers to analyze the low-level events within their multiprocessor systems. With the profiling architecture, it is possible to monitor all processors and system-wide events concurrently in a prototyping multiprocessor system. In addition, our design is less intrusive to the target system design since new instructions or extra dedicated bus are not necessary. Therefore our lightweight architecture keeps the design as simple and as small as possible. We implement this architecture into the Gaisler Leon3 open source embedded platform and realize the multiprocessor system on a Xilinx ML501 FPGA board. Evaluation results show that the proposed architecture is able to extract the low-level events, which help programmers to characterize target applications more easily and have sufficient information to find the performance bottlenecks while, and it meets the requirements of simple, flexible, and less intrusive design.
[1] Luca Benini, David Bertozzi, Alessandro Bogliolo, Francesco Menichelli, Mauro Olivieri, “MPARM: Exploring the Multi-processor SoC Design Space with SystemC”, Journal of VLSI Signal processing, Volume: 41, Page(s): 169-182, 2005.
[2] Wander O. Cesario, Amer Baghdadi, Lovic Gauthier, Damien Lyonnard, Gabriela Nicolescu, Yanick Paviot, Sungjoo Yoo, Ahmed A.Jerraya, Mario Diaz-Nova ,“Multiprocessor SoC Platforms: A Component-Based Design Approach”, IEEE Trans. on Design and Test, Nov-Dec 2002.
[3] Jonathan Corbet, Greg Kroah-Hartman, and Alessandro Rubini, Linux Device Drivers, 3rd ed. Sebastopol: O’Reilly, 2005.
[4] Multiprocessor Systems-on-Chip, Ed. Ahmed Jerraya, Wayne Wolf, San Francisco California: Elsevier Morgan Kaufmann, 2005.
[5] Peter S. Magnusson, Magnus Christensson, Jesper Eskilson, Daniel Forsgren, Gustav H□llberg, Johan H□gberg, Fredrik Larsson, Andreas Moestedt, Bengt Werner, “Simics: A Full System Simulation Platform”, IEEE Trans. on Computer, Volume: 35 Issue: 2, Feb 2002.
[6] Erno Salminen, Ari Kulmala, and Timo D. H□m□l□inen, “HIBI-based Multiprocessor SoC on FPGA”, Proc. IEEE International Symposium on Circuits and Systems (ISCA2005), Volume: 4, Page(s): 3351-3354, May 2005.
[7] Mohammed El Shobaki and Lennart Lindh, “A Hardware and Software Monitor for High-Level System-on-Chip Verification”, Proc. IEEE International Symposium on Quality Electronic Design. San Jose, USA, March 2001.
[8] Brinkley Sprunt, “Pentium 4 Performance-Monitoring Features”, IEEE Micro, Volume: 22 Issue: 4 Page(s): 72-82, July-Aug 2002.
[9] Brinkley Sprunt, “The Basics of Performance-Monitoring Hardware”, IEEE Micro, Volume: 22 Issue: 4 Page(s): 64-71, July-Aug 2002.
[10] ARM limited, AMBA Specification 2.0, http://www.arm.com
[11] Jiri Gaisler, GRLIB IP cores Manual, http://www.gaisler.com
[12] Jiri Gaisler, GRMON User's Manual, http://www.gaisler.com
[13] Jiri Gaisler, The LEON3 Processor User's Manual, http://www.gaisler.com
[14] Daniel Hellstr□m, Snapgear for LEON manual, http://www.gaisler.com
[15] IBM, Device Control Register Bus 3.5 Architecture Specifications, http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/
2F9323ECBC8CFEE0872570F4005C5739.
[16] IBM, PLB Performance Monitor User’s Manual, http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/
904F6514C02DC4D487256B9E0054315D.
[17] Inc. SPARC International, SPARC Architecture Manual Version 8, http://www.sparc.org/standards/v8.pdf.
[18] Intel, 3rd Generation Intel Xscale Microarchitecture Developer's Manual, http://developer.intel.com/design/intelxscale/316283.htm.
[19] Hassan Shojania, Hardware-based performance monitoring with VTune Performance Analyzer under Linux, http://hassan.shojania.com.
[20] Xilinx, ML501 Evaluation platform User Guide, http://www.xilinx.com/products/boards/ml501/docs.htm.
[21] 陳章龍, 嵌入式技術與系統:INTEL XSCALE結構與開發, 文魁資訊股份有限公司, Page(s): 4-49, 2006.