使用氮化矽做電荷儲存層之電荷陷阱式快閃記憶體，許多問題無法滿足元件微縮發展的趨勢，因此利用高介電係數材料取代氮化矽結構作為電荷儲存層之電荷陷阱式快閃記憶體元件是未來發展的趨勢。然而傳統以二氧化鉿作為儲存層的TAHOS元件結構，亦存在許多問題而無法滿足元件特性上的要求，因此便引進了堆疊式電荷儲存層結構以提升元件操作效能。本實驗使用核研所浸潤式離子佈植機，以不同的氮摻雜時間及退火溫度，氮化元件的高介電係數材料。研究主要是利用氮化後的特性，配合堆疊的結構，藉著電荷陷阱密度的多寡、能階大小的改變、K值影響分壓的不同、陷阱能階等種種特性，達成各項操作特性的提升。本論文研究的方向主要分為下列三大方向:
1.利用PIII電漿離子將氮摻雜於氧化鉿鋁與二氧化鉿之多層電荷儲存層的技術，探討改變氮化時間且相同退火溫度處理後，氮元素在氧化鉿鋁與二氧化鉿之多層電荷儲存層中的分佈情況對於電荷陷阱式快閃記憶體操作特性的影響。實驗結果顯示，氮摻雜於氧化鉿鋁與二氧化鉿之多層電荷儲存層中最佳的氮化時間為30分鐘，在寫入/抹除速度、電荷保持力與耐力方面，都有明顯提升。
2.利用PIII電漿離子的技術，將前一章中最佳的氮摻雜時間，應用於氧化鉿鋁與二氧化鉿之多層電荷儲存層中，再配合不同的退火溫度處理後，釐清氮元素在氧化鉿鋁與二氧化鉿之多層電荷儲存層中的分佈情況，且探討此氮元素分佈狀況對電荷陷阱式快閃記憶體操作特性的影響。由實驗得知，利用PIII電漿離子氮摻雜30分鐘且經過900℃/30秒退火溫度處理後，氮元素分佈在氧化鉿鋁中的量會比分佈在二氧化鉿中還要多，在寫入/抹除速度、電荷保持力與耐力方面都會有比較好的表現。
3.本章以Si3N4/Al2O3/HfO2堆疊式電荷儲存層結構為基礎，分成兩個實驗部分，第一部分實驗為：改變Si3N4/Al2O3/HfO2堆疊式電荷儲存層之中間阻擋層Al2O3的厚度，探討此變化對電荷陷阱式快閃記憶體操作特性的影響，且找出最佳化之Si3N4/Al2O3/HfO2堆疊式電荷儲存層之中間阻擋Al2O3厚度的參數。由實驗結果得知，Si3N4/Al2O3/HfO2堆疊式電荷儲存層之中間阻擋層Al2O3為30Å的厚度時，在操作寫入/抹除時，第一層Si3N4與第三層HfO2之電荷儲存層對於捕捉載子的情況可以發揮最大的效應，使得寫入/抹除速度最快，且此厚度對於電荷保持力與耐力方面也會比較優異；第二部分實驗為：利用本章第一部分實驗中，Si3N4/Al2O3/HfO2堆疊式電荷儲存層之中間阻擋層Al2O3最佳化之30Å的厚度，繼續作延伸與探討，使用Si3N4/Al2O3/HfO2堆疊式電荷儲存層之中間阻擋層Al2O3最佳化的參數，改變Si3N4/Al2O3/HfO2堆疊式電荷儲存層中Si3N4與HfO2兩層電荷儲存層的厚度，探討此堆疊結構對電荷陷阱式快閃記憶體操作特性的影響。實驗結果顯示，第一層Si3N4的厚度為30Å與第一層Si3N4的厚度為40Å相較起來，30Å的Si3N4會使得堆疊式電荷儲存層之中間阻擋層Al2O3比較靠近穿隧氧化層，因此對於寫入/抹除速度會比較有利，且在電荷保持力與耐力方面此結構之厚度的表現還是較佳。
由實驗結果可發現，引進PIII電漿離子氮化技術，使用最佳化的氮摻雜時間與最佳化的退火溫度處理配合之，應用於氧化鉿鋁與二氧化鉿電荷儲存層，將有效地提升電荷陷阱式快閃記憶體中各種操作特性；另外，在Si3N4/Al2O3/HfO2堆疊式電荷儲存層結構中，Si3N4/Al2O3/HfO2堆疊式電荷儲存層之中間阻擋層Al2O3與第一層Si3N4之電荷儲存層有最佳化厚度之參數，此參數對於電荷陷阱式快閃記憶體可以有最好的操作特性。

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