摘要
此論文中，前兩個研究主題為V-Band的低雜訊放大器(Low Noise Amplifier LNA)，低雜訊放大器顧名思義在設計上最要的兩個重點就是雜訊(Noise)跟增益(Gain)，所以在此論文中的前兩個主題中，第一個就是增益為主、第二個主題就以雜訊為主的研究，而在最後一個主題中的毫米波接收器前端(低雜訊放大器與混波器)所採用的低雜訊放大器，將會結合前兩個主題的研究。

在目前隨著先進製程的演進，與產品追求低功率消耗的情況下，追求供應電壓以成為顯學，所以捨棄了疊接(Cascode)這種需要較高供應電壓的技巧，而近年來為了節省面積、與系統設計提升電路表現所常被提及的SoC的觀念下，單純只使用串接(Cascade)架構，會造成需要大量面積的方式，也不將被採納在此研究中，而為了SoC，此研究用tSMC CMOS 90nm製程實作63 GHz 低雜訊放大器，所以在第一個主題中的研究中將採用正回授的架構，最後成功的實現最大增益在63 GHz為20 dB、頻帶內最低雜訊因子為4.6 dB、-3 dB 頻寬為7GHz，Noise Measure為1.903、IIP3為-11 dBm、OP1dB為-5 dBm、功率消耗為10 mW、供應電壓為1.2 V，晶片面積為0.48 mm2的低雜訊放大器。

在第二個主題中，將會研究與分析如何採用圖解法，去選擇電晶體的尺寸與偏壓，以實現串接架構的低雜訊放大器有較低的雜訊因子，最後成功的實現最大增益在71 GHz為16 dB，頻帶內最低雜訊因子為3.5 dB，-3 dB 頻寬為13.5 GHz，Noise Measure為1.271、IIP3為-3 dBm，OP1dB為-0.16 dBm，功率消耗為9 mW，供應電壓為1.2V，晶片面積為0.667 mm2的低雜訊放大器。

在最後一個主題中，延續第一個主題為了SoC對於面積要小的要求下，選擇了Direct-Conversion的架構，以減少大量的串接，在低功率消耗方面，低雜訊放大器採用第一個主題中的正回授架構，而混波器的選擇採用不需要功率消耗的被動混波器，被動混波器同時也提供良好的線性度，最後成功的實現最大增益23 dB在LO頻率為63 GHz，頻帶內最低雜訊因子為4.7 dB(DSB )、7.8 dB(SSB)，-3 dB 頻寬為0~1.8 GHz，IP1dB為-25.5 dBm，功率消耗為10 mW，供應電壓為1.2 V，晶片面積為0.48 mm2的毫米波接收器前端。

Abstract
In this thesis, there are three topics. First two topics focus on the analysis and design of V-Band low noise amplifiers (LNAs). Gain and noise figure are the key index of LNAs. In the first work we improve the gain performance of LNA by positive feedback and a design procedure for low noise figure is proposed in the second work. The last topic, combining the former works, demonstrates a millimiter-wave receiver front-end with the former advantages.

Low power supply is more and more important in the advanced silicon technologies and circuit designs. In chapter-II (the first topic), LNA with positive feedback technique is presented. The positive feedback avoids a large number of cascaded stages and the common-source topology is suitable for low-power operation. The proposed LNA, fabricated in tsmc 90-nm CMOS technology, shows a peak gain of 20 dB at 63 GHz with a 7 GHz 3-dB bandwidth and a noise measure of 1.903, IIP3 of -11dBm, OP1dB of -5 dBm while consuming a dc power of 10 mW from a 1.2 V supply voltage.

In chapter-III (the second topic), A graphical method is proposed to select the sizes of transistors in each stage for lowering the NF of LNAs. The proposed LNA, fabricated in tsmc 90-nm CMOS technology, shows a peak gain of 16 dB at 71 GHz with a 13.5 GHz 3-dB bandwidth and a noise measure of 1.271, IIP3 of -3dBm, OP1dB of -0.16 dBm while consuming a dc power of 9 mW from a 1.2 V supply voltage.

In chapter-IV, a direct-conversion receiver is proposed with the positive feedback LNA and the passive mixer. The low-power performance is achieved by the proposed LNA topology and the passive mixer consuming no dc current. The passive mixer shows no flicker noise and good linearity due to its passive operation. The proposed receiver front-ends, fabricated in tsmc 90-nm CMOS technology, shows a peak gain of 23 dB at 63 GHz with a 3.6 GHz 3-dB bandwidth, IP1dB of -25.5 dBm while consuming a dc power of 9.6 mW from a 1.2 V supply voltage.

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